Optimized Memory Allocation and Power Minimization for FPGA-Based Image Processing

Abstract

Memory is the biggest limiting factor to the widespread use of FPGAs for high-level image processing, which require complete frame(s) to be stored in situ. Since FPGAs have limited on-chip memory capabilities, efficient use of such resources is essential to meet performance, size and power constraints. In this paper, we investigate allocation of on-chip memory resources in order to minimize resource usage and power consumption, contributing to the realization of power-efficient high-level image processing fully contained on FPGAs. We propose methods for generating memory architectures, from both Hardware Description Languages and High Level Synthesis designs, which minimize memory usage and power consumption. Based on a formalization of on-chip memory configuration options and a power model, we demonstrate how our partitioning algorithms can outperform traditional strategies. Compared to commercial FPGA synthesis and High Level Synthesis tools, our results show that the proposed algorithms can result in up to 60% higher utilization efficiency, increasing the sizes and/or number of frames that can be accommodated, and reduce frame buffers’ dynamic power consumption by up to approximately 70%. In our experiments using Optical Flow and MeanShift Tracking, representative high-level algorithms, data show that partitioning algorithms can reduce total power by up to 25% and 30%, respectively, without impacting performance.

Fast and memory efficient de-hazing technique for real-time computer vision applications

“…To address this issue, assume that the ' X ' image or frame will be stored as an array (A) of 8-bit elements. The 'A' array has columns and rows and is usually stored in BRAM [11] like a row by row or a column by column manner (ixj). Generally, the computer or processor does not keep track of each element of an array's address.…”

Encoding of Terms in EMB-Based Mealy FSMs

“…As a rule, it is very important to choose the state codes leading to minimizing the values of L( f i ) [8]. There are a lot of methods of state assignment targeting FPGA-based design [17][18][19][20][21]24,25]. There is an opinion that JEDI [8] is the best of them [4].…”

Image Processing Using FPGAs

“…Garcia et al [ 2 ] worked on the thesis that the image processing operations which require random access to the whole frame (including iterative algorithms) are particularly difficult to realise in FPGAs. They investigate the mapping of a frame buffer onto the memory resources of an FPGA, and explore the optimal mapping onto combinations of configurable on-chip memory blocks.…”