Optimization of threshold logic networks with ODC-based node merging

In this article, we present an optimization method for threshold logic networks (TLNs) based on observability don’t-care-based node merging. To reduce gate count in a TLN, it iteratively merges two gates that are functionally equivalent or whose differences are never observed at the primary outputs. Furthermore, it is able to identify redundant wires and replace wires for removing more gates. Basically, the proposed method is primarily adapted from an ATPG-based node-merging approach which works for conventional Boolean logic networks. To extend the approach for TLNs, we develop a method for computing mandatory assignments of a stuck-at fault test on a threshold gate and a method for conducting logic implication in a TLN. Additionally, to achieve a better optimization quality, we integrate the proposed method with other optimization methods. The experimental results show that the overall optimization method can save an average of approximately 4.7% threshold gates for a set of TLNs which are generated by using the latest TLN synthesis method. The experimental results also demonstrate the efficiency of the optimization method.

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Optimization of threshold logic networks with ODC-based node merging

Cited by 2 publications

References 13 publications

Don’t-Care-Based Node Minimization for Threshold Logic Networks

Don’t-Care-Based Node Minimization for Threshold Logic Networks

Optimization of Threshold Logic Networks with Node Merging and Wire Replacement

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