Optimization of Silicon MZM Fabrication Parameters for High Speed Short Reach Interconnects at 1310 nm

Abstract

Abstract:Optical modulators are key components to realize photonic circuits, and Mach-Zehnder modulators (MZM) are often used for high speed short reach interconnects. In order to maximize the tolerable path loss of a transmission link at a given bitrate, the MZM needs to be optimized. However, the optimization can be complex since the overall link performance depends on various parameters, and, for the MZM in particular, implies several trade-offs between efficiency, losses, and bandwidth. In this work, we propose a general and rigorous method to optimize silicon MZM. We first describe the optical link, and the numerical method used for this study. Then we present the results associated to the active region for 1310 nm applications. An analytical model is generated, and allows us to quickly optimize the p-n junction depending of the targeted performances for the MZM. Taking into account the required optical link parameters, the maximum tolerable path losses for different length of MZM is determined. By applying this method, simulations show that the optimum MZM length for 25 Gbps applications is 4 mm with an efficiency of 1.87 V·cm, 0.52 dB/mm of losses. A tolerable path loss of more than 25 dB is obtained.

Compact and Energy-Efficient Forward-Biased PN Silicon Mach-Zehnder Modulator

“…The waveguide width is 460 nm, constructed with an asymmetric PN structure, having 330 nm of P-doped and 130 nm of N-doped region. The asymmetric PN structures, with a wider P-doped area, are more efficient in terms of modulation efficiency since the holes have a higher impact on the free carrier index change [32]. To evaluate this statement, the changes in the electron and hole concentrations versus the position across the PN junction, considering 1.0 V of applied DC bias voltage for three combinations of widths of the P and N doped regions for the PN junction, are presented in Fig.…”

Improvement of critical temperature of niobium nitride deposited on 8-inch silicon wafers thanks to an AlN buffer layer

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