Optimization of high order control including overlay, alignment, and sampling

Choi, DongSub; Lee, Chul Seung; Bang, Changjin; Cho, Daehee; Gil, Myunggoon; Izikson, Pavel; Yoon, Seunghoon; Lee, Dohwa

doi:10.1117/12.772274

Cited by 11 publications

(4 citation statements)

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“…However, the sensitivity to the process variability remains as a hurdle to be tackled and part of this is compensated by the overlay reading after the pattern printing. With the adoption of the high order correction on the scanner, the overlay control improves up to 100% comparing to the baseline linear method [2][3] and the measurement points are grown from 2 to 4-digits sampling. Accordingly, throughput improvement on overlay measurement has been driven, too.…”

Section: Introductionmentioning

confidence: 99%

SEM ADI on device overlay: the advantages and outcome

Kim

Park

et al. 2023

Metrology, Inspection, and Process Control XXXVII

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The advanced logic node is continuously shrinking toward sub-nm node and EUV lithography is the one of main drivers to reach better patterning resolution resulting in reduced process steps. Along with this design rule shrink, On Product Overlay (OPO) requirement has been critical to the device yield making the accuracy and stability of optical overlay measurement to become primary concern on the lithography process control. Historically Optical Microscope (OM) ADI overlay was accepted and the standard for control to meet OPO requirements. Along the past years, as OPO budget diminishes with node-to-node, OM overlay required additional supporting reference data to compensate the inherent accuracy problem. Industry adopted the accuracy correction knob with High Voltage SEM (HV-SEM) at post etch, also known as SEM AEI overlay. The SEM AEI overlay measures the error contribution of different process influence and the overlay mark to real device pattern overly bias together. The inaccuracy of OM ADI overlay has been treated as a non-correctable error components till the on-device overlay measurement of HV-SEM after etching was enabled to compensate the delta known as Non-Zero Offset (NZO) or Mis-Reading Correction (MRC). Today the HV-SEM on-device overlay measurement at AEI is widely adopted as one of critical component to meet the OPO requirement enabling scaling for all types of advanced CMOS devices production. The main driver of On-Device-Overlay (ODO) measurement at AEI step is the see-through imaging capability to see all relevant layers through the stack even though the measurement step/time differs on the same wafer of the ADI optical overlay measurement are ranging from few to two-digit days depending on the process complexity. There has been an increasing need for a faster response of overlay measurements to close the overlay control loop and breakdown the device to target error versus the process overly induce component – in other words, to correct in the right step. This leads to the necessity of SEM ADI overlay measurement. With the recent e-Beam evolution of more higher landing energy, probe current and improved Total Measurement Uncertainty (TMU) performance, SEM ADI overlay measurement is enabled and considered to show the performances to meet market requirements on the selected layers of interest. In this paper, we would like to demonstrate the enablement of SEM ADI overlay measurement including the accuracy comparison with OM ADI overlay on the DBO scribe target versus real device pattern measurement performance. With SEM ADI and AEI overlay measurement on the same patterns, we could also demonstrate the error breakdown between optical target to device and from ADI to AEI process induced error which will enable the better correctable methodology to minimize NZO/MRC. In addition, this process contribution to error breakdown could be extended to improve, in the future, the Edge Placement Error (EPE) control.

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Section: Introductionmentioning

confidence: 99%

SEM ADI on device overlay: the advantages and outcome

Kim

Park

et al. 2023

Metrology, Inspection, and Process Control XXXVII

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“…In this paper, the impact of TMU on overlay error correction, which includes process and measurement noise, is investigated in terms of the stability of high-order correction parameters. [3][4][5][6] By evaluating the variation range of correctable parameters as a figure of merit, a practical TMU is determined for a given design rule. Our methodology is described and our simulation results are discussed.…”

Section: Introductionmentioning

confidence: 99%

Impact of total measurement uncertainty on overlay error correction

Shin

Yeo

Kang

et al. 2010

J. Micro/Nanolith. MEMS MOEMS

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The objective of this work is to determine a guideline for defining practical overlay metrology requirements for a given design rule. Total measurement uncertainty ͑TMU͒ of overlay metrology is defined as the square root of square sum of the following items: the mean of the tool-induced shift ͑TIS͒, TIS 3-sigma, dynamic precision, and tool-to-tool matching. The TMU is dependent upon process conditions, so TMU is different by process layer. In this study, the impact of TMU on overlay error correction, which includes process and measurement noise, is investigated in terms of the stability of high-order overlay correction parameters. By evaluating the variation range of correctable parameters as a figure of merit, the corresponding TMU is determined for a given design rule. Utilizing this methodology, we determined that 2 nm of TMU value is the allowable limit for 45 nm of dynamic random access memory ͑DRAM͒ half pitch based upon simulation results. Similarly, we recommend 1 nm of TMU for 36 nm of DRAM half pitch. Our methodology is described and our simulation results are discussed.

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“…In recent years, the industry has moved toward high-order overlay modeling and more sophisticated alignment strategies, which requires more overlay sampling and excessive alignment [7][8][9][10][11]. For example, the work in [11] suggests high-order process control by overlay control with one model per lot or one model for every wafer; the work in [7] proposes high-order wafer alignment, while the work in [9] proposes exposure tool characterization using offline overlay sampling. These improvements in overlay control are capable of reducing overlay errors considerably (by up to 30% [7,9]) when a high-order overlay model is used.…”

Section: Introductionmentioning

confidence: 99%

A framework for exploring the interaction between design rules and overlay control

Ghaida

Gupta

2013

SPIE Proceedings

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Overlay control is becoming increasingly more important with the scaling of technology. It has become even more critical and more challenging with the move toward multiple-patterning lithography, where overlay translates into CD variability. Design rules and overlay have strong interaction and can have a considerable impact on the design area, yield, and performance. This paper offers a framework to study this interaction and evaluate the overall design impact of rules, overlay characteristics, and overlay control options. The framework can also be used for designing informed, design-aware overlay metrology and control strategies. In this work, The framework was used to explore the design impact of LELE double-patterning rules and poly-line end extension rule defined between poly and active layer for different overlay characteristics (i.e., within-field vs. field-to-field overlay) and different overlay models at the 14nm node. Interesting conclusions can be drawn from our results. For example, one result shows that increasing the minimum mask-overlap length by 1nm would allow the use of a thirdorder wafer/sixth-order field-level overlay model instead of a sixth-order wafer/sixth-order field-level model with negligible impact on design.1

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Optimization of high order control including overlay, alignment, and sampling

Cited by 11 publications

References 0 publications

SEM ADI on device overlay: the advantages and outcome

SEM ADI on device overlay: the advantages and outcome

Impact of total measurement uncertainty on overlay error correction

A framework for exploring the interaction between design rules and overlay control

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