Optimization of Communication Schemes for DMA-Controlled Accelerators

Wang, Jooho; Park, Sungkyung; Park, Chester Sungchung

doi:10.1109/access.2021.3118094

Cited by 4 publications

References 51 publications

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Spatial Data Dependence Graph Based Pre-RTL Simulator for Convolutional Neural Network Dataflows

Wang

Park

2022

IEEE Access

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In this paper, a new pre-RTL simulator is proposed to predict the power, performance, and area of convolutional neural network (CNN) dataflows prior to register-transfer-level (RTL) design. In the simulator, a novel approach is adopted to implement a spatial data dependence graph (SDDG), which enables us to model a specific dataflow alongside inter-instruction dependencies by tracking the status of each processing element (PE). In addition, the proposed pre-RTL simulator makes it possible to evaluate the impact of memory constraints such as latency and bandwidth. The latency-insensitive and bandwidth-insensitive PE controllers assumed in the proposed pre-RTL simulator guarantee both operational correctness and maximum performance, regardless of memory constraints. In particular, it is shown that the optimal distribution method of local memory bandwidth can reduce the accelerator performance by up to 37.6% compared with the equal distribution method. For weight stationary (WS) and row stationary (RS) dataflows, the accelerator performance closely depends on memory constraints. The simulation results also show that the relative performances of dataflows depend on the layer shape of the convolutional layer. For example, for an identical hardware area in a standard convolutional layer of AlexNet, WS dataflows do not provide any performance gain over RS dataflows when the memory latency is sufficiently high. In addition, WS dataflows cannot fully reuse the input activation, thereby increasing local memory accesses, since the number of weights loaded at a specific time is limited. Moreover, in a depth-wise convolutional layer of MobileNet, WS dataflows tend to outperform RS dataflows even in the presence of large memory latency.

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Spatial Data Dependence Graph Based Pre-RTL Simulator for Convolutional Neural Network Dataflows

Wang

Park

2022

IEEE Access

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Modeling and Simulation of System Bus and Memory Collisions in Heterogeneous SoCs

et al. 2022

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A system simulator is proposed and developed, which can help to optimize design parameters and hence minimize the number of collisions. In order to search the optimal design parameter combination which meets the user requirement, the proposed simulator has some knobs: partitioning between software and hardware, scheduling the operations in the system, and memory merging, all of which can be adjusted to predict collisions and search the optimal architecture. Also, design parameters can be adjusted sequentially to cover all design options and estimate the predicted performance for each option. The proposed system simulator is evaluated with an example signal processing algorithm, orthogonal matching pursuit (OMP) algorithm. Performances of four cases of the OMP algorithm are predicted by the proposed simulator and in turn are compared with the actual performances on ZedBoard. The proposed simulator can predict the performance of heterogeneous systems on chips with under 5% error for all the candidate architectures for OMP while taking the system bus and memory conflicts into account. Moreover, the optimized heterogeneous SoC architecture for the OMP algorithm improves performance by up to 32% compared with the conventional CAG-based approach. The proposed simulator is verified that the proposed performance estimation algorithm is generally applicable to estimate the performance of any heterogeneous SoC architecture. For example, the estimation error is measured to be no more than 5.9% for the convolutional layers of CNNs and no more than 5.6% for the LDPC-coded MIMO-OFDM. In addition, the optimized heterogeneous SoC architecture improves performance by up to 48% for the third convolutional layer of AlexNet and 56% for the LDPC-coded MIMO-OFDM. Lastly, compared with the conventional simulationbased approaches, the proposed estimation algorithm provides a speedup of one to two orders of magnitudes.

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CryptoMMU: Enabling Scalable and Secure Access Control of Third-Party Accelerators

Alam,

Lee,

Bhattacharjee

et al. 2023

56th Annual IEEE/ACM International Symposium on Microarchitecture

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Optimization of Communication Schemes for DMA-Controlled Accelerators

Cited by 4 publications

References 51 publications

Spatial Data Dependence Graph Based Pre-RTL Simulator for Convolutional Neural Network Dataflows

Spatial Data Dependence Graph Based Pre-RTL Simulator for Convolutional Neural Network Dataflows

Modeling and Simulation of System Bus and Memory Collisions in Heterogeneous SoCs

CryptoMMU: Enabling Scalable and Secure Access Control of Third-Party Accelerators

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