Optimization of cascode CMOS low noise amplifier using inter-stage matching network

A High Gain Broadband Low Noise Amplifier for Wireless Networks

“…One of the best criteria for comparison of LNAs performances is figure of merit (FOM) formulas. A conventional formula [17] for FOM is described in (5). In this relation, F, is noise figure and Pd, is DC power consumption of LNA [17].…”

“…E.g. in [5], in the design of a LNA, the conventional cascode architecture is assumed such as two-stage amplifier and result in an inter-stage impedance matching network is employed [5]. In [6], design of cascode amplifier in the frequency of 60 GHz by CMOS process is reported, the amplifier is implemented using an inter-stage impedance matching network, this network, improve the power gain and make an excellent impedance matching between the CS and the CG devices [6].In the second section of this paper, matching networks structure is discussed.…”

Cascode Current Mirror for a Variable Gain Stage in a 1.8 GHz Low Noise Amplifier (LNA)

“…This amplifier is matched internally using two spiral inductors and a capacitor. By inserting just a single inductor acting as an inter-stage matching network, a 2-GHz LNA can also be optimized [7]. On the other hand, a high-Q active inductor is introduced into a 1.75-GHz CMOS LNA to reduce the area of chip and the complexity [8].…”

An 8 GHz Variable Gain Low Noise Amplifier (VGLNA) Utilizing Parallel Inter-Stage Resonance

“…The cascode structure used in the LNA is to reduce Miller effect on input impedance and improve reverse isolation. An inter-stage matching network is applied in the cascode structure between the two stage amplifier in [3] and [4] to provide better performance. A mutual coupling between degeneration and inter-stage inductors is employed as an alternative to implement input impedance matching [5].…”