Optimization of a Hetero-Structure Vertical Tunnel FET for Enhanced Electrical Performance and Effects of Temperature Variation on RF/Linearity Parameters

Vanlalawmpuia, K.; Bhowmick, Brinda

doi:10.1007/s12633-020-00411-7

Cited by 16 publications

(4 citation statements)

References 35 publications

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“…The extrapolated input voltage known as VIP 3 [42] is the third-order harmonic voltage equals the fundamental voltage and is evaluated as in equation (12). 13) [43]. It can be concluded that IIP 3 exhibits significant fluctuations with temp.…”

Section: Temperature Dependence Of Linearity Parametersmentioning

confidence: 99%

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Investigating temperature reliability of RF performance metrics and linearity for double gate doping less TFET

Dewan,

Chaudhary,

Singh

et al. 2024

Eng. Res. Express

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The Doping Less Tunnel Field Effect Transistor (DL-TFET) is gaining recognition as a promising TFET structure due to its resistance to random dopant fluctuations (RDFs) and the elimination of high thermal budgets and costly annealing techniques. However, temperature sensitivity remains a critical factor in assessing the device’s reliability, as the bandgap of the semiconductor material (Eg) varies with temperature fluctuations. Therefore, this study investigates the impact of temperature changes (ranging from 240 to 360 Kelvin) on thelinearity and RF/analog characteristics of a Heterojunction (HJ), Double Gate (DG), Doping Less (DL) TFET.The analysis encompasses various RF/analog and DC parameters, including ID − VG characteristics, ID − VD characteristics, gm (transconductance), gd (output conductance), fT (cut-off frequency), GBP (Gain Bandwidth Product), TGF (transconductance generation factor), and TFP (transconductance frequency product). These parameters are evaluated using the ATLAS simulation tool, taking into account the influence of temperature fluctuations. Furthermore, the study considers temperature variations when assessing linearity characteristics such as the second-order Voltage Intercept Point (VIP2), third-order Voltage Intercept Point (VIP3), intermodulation distortion (IMD3), and third-order input interception point (IIP3).

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Section: Temperature Dependence Of Linearity Parametersmentioning

confidence: 99%

“…he IMD 3 response to various temp. is shown in figure 14(b).To improve system linearity and reduce signal distortion, IMD 3 must be minimal [43]. There is a significant variation in IMD 3 for low V gs , and it rises with rising temp.…”

Section: Temperature Dependence Of Linearity Parametersmentioning

confidence: 99%

Investigating temperature reliability of RF performance metrics and linearity for double gate doping less TFET

Dewan,

Chaudhary,

Singh

et al. 2024

Eng. Res. Express

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“…Manas et al [20] analyses the vertically grown GaSb/Si TFET with a source pocket to improve the device performance. Heterostructure vertical TFET proposed by [21] shows higher drive current due to alignment of gate electrostatic field with electrons tunnelling direction. Further, to suppress the ambipolar current, wide bandgap materials are incorporated on channel and drain regions [22].…”

Section: Introductionmentioning

confidence: 99%

Temperature impact on device characteristics of charge plasma based tunnel FET with Si_0.5Ge_0.5 source

et al. 2021

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In this work, the impact of temperature is investigated on the electrical characteristics of charge plasma-based doping-less double gate tunnel FET (DL-DG-TFET) with a low bandgap source material i.e., Si0.5Ge0.5. The influence of temperature (from 250 K to 450 K) is analysed on several performance parameters of the device such as bandgap, threshold voltage, SS, switching current ratio, ID-VGS, ID-VDS, gate current. The small change in energy bandgap with temperature reflects that device is minimally dependent on temperature. Temperature impact is significant on the sub-threshold region of transfer characteristics due to SRH recombination and trap-assisted tunnelling current. Insignificant variation of gate current with temperature signifies the better reliability of the device. Further, temperature effect is observed on analog parameters such as cut-off frequency, gate capacitance, trans-conductance, output conductance, power delay product (PDP). The minimal variation of analog parameters with temperature assures application of device in high-temperatures.

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“…Pocket implantation technique is another dominating choice to enhance device performance but, this generates large drain induced threshold voltage shift and low output resistance, which is not suited for application in high performance analog circuits [12][13][14], thereby discarded at many instances.…”

Section: Introductionmentioning

confidence: 99%

Physics and Modelling of Tri-Layered Strained Channel for Development of Double Gate n-channel FET

Kumar

Dhar

2021

Preprint

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The strain silicon technology with FET is a dominant technology providing enrichment in carrier velocity in nanoscaled device by change of band structure arrangement. Leakage reduction while enhancement in drain current is another major objective therefore, designing a nano-regime double gate FET with strained channel is perceived. So, design and implementation of a double gate strained heterostructure on insulator (DG-SHOI) FET with tri-layered channel (s-Si/s-SiGe/s-Si) is the core. Biaxial strain is created in channel by inculcating three layers with optimal thicknesses while narrow channel depletion regions are strongly controlled by equipotential gates. Consequently, maximum charge carriers accumulate in channel due to quantum carrier confinement instigating ballistic transport across the 22 nm channel length device leading to lessening of intervalley scattering. In comparison to existing 22 nm DGSOI FET, drain current augmentation of 56% and transconductance amplification of 87.6% is observed while DIBL is prudently reduced for this newly designed and implemented DG-SHOI FET, signifying advancement in microelectronic technology.

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Optimization of a Hetero-Structure Vertical Tunnel FET for Enhanced Electrical Performance and Effects of Temperature Variation on RF/Linearity Parameters

Cited by 16 publications

References 35 publications

Investigating temperature reliability of RF performance metrics and linearity for double gate doping less TFET

Investigating temperature reliability of RF performance metrics and linearity for double gate doping less TFET

Temperature impact on device characteristics of charge plasma based tunnel FET with Si_0.5Ge_0.5 source

Physics and Modelling of Tri-Layered Strained Channel for Development of Double Gate n-channel FET

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Optimization of a Hetero-Structure Vertical Tunnel FET for Enhanced Electrical Performance and Effects of Temperature Variation on RF/Linearity Parameters

Cited by 16 publications

References 35 publications

Investigating temperature reliability of RF performance metrics and linearity for double gate doping less TFET

Investigating temperature reliability of RF performance metrics and linearity for double gate doping less TFET

Temperature impact on device characteristics of charge plasma based tunnel FET with Si0.5Ge0.5 source

Physics and Modelling of Tri-Layered Strained Channel for Development of Double Gate n-channel FET

Contact Info

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Temperature impact on device characteristics of charge plasma based tunnel FET with Si_0.5Ge_0.5 source