Optimization of a 0.18 μm 1.5 V CMOS technology to achieve 15 ps gate delay

Yang, I.Y.; Gilbert, P.; Pettinato, C.; Anderson, S. G.; Woodruff, Robert W.; Misra, Veena; Bhat, Naagesh S.; Reid, K.; Lii, T.; Yuan, Can; Dyer, D.; O'Meara, David; Collins, Sean; De, Han; Veeraraghavan, S.

doi:10.1109/vlsit.1998.689235

Cited by 3 publications

(1 citation statement)

References 1 publication

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“…can be expressed as (2), where capacitance components are extracted using areal and peripheral intensive capacitor patterns at zero bias, as summarized in Table I. Especially, is extracted using a field solver (Raphael) calibration based on SEM data.…”

Section: Experiments and Discussionmentioning

confidence: 99%

Characterization of channel width dependence of gate delay in 0.18-μm CMOS technology

Park

Lee²,

Jang³

1999

IEEE Electron Device Lett.

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The channel width dependence of gate delay in 0.18-m CMOSFET has been characterized. Substantial increase of gate delay observed in the narrow channel width region is found due to channel width independent capacitance components, which is inherent to transistors. An expression for gate delay considering the channel width independent capacitance components and gate sheet resistance is derived and compared with experimental data. The minimum gate delay is shown to result from the compromise between delay components proportional to channel width and proportional to inverse of channel width. Although the channel width independent capacitance is negligible in the wide channel width region, the gate delay of the 1-m channel width ring oscillator increased more than 20% compared with the 5-m channel width ring oscillator.Index Terms-Channel width independent capacitance, gate delay, gate sheet resistance, 0.18-m CMOSFET.

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Section: Experiments and Discussionmentioning

confidence: 99%

Characterization of channel width dependence of gate delay in 0.18-μm CMOS technology

Park

Lee²,

Jang³

1999

IEEE Electron Device Lett.

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show abstract

Verification of overlap and fringing capacitance models for MOSFETs

Wakita

Sato

2000

Solid-State Electronics

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Optimization of implant anneals to improve transistor performance in a 0.15 μm CMOS technology

Lutze

Miranda²,

Scott³

et al. 2000

IEEE Electron Device Lett.

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The impact of including a rapid thermal anneal step after the extension implants is examined for a 0.15 m CMOS process. SIMS data will verify that shallower junctions can be obtained with only a single anneal cycle after the source-drain implants, implying that transient enhanced diffusion is minimal for this technology. Further, transistor data indicates that improved CMOS device performance can be obtained without the extension anneal cycle.

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Optimization of a 0.18 μm 1.5 V CMOS technology to achieve 15 ps gate delay

Cited by 3 publications

References 1 publication

Characterization of channel width dependence of gate delay in 0.18-μm CMOS technology

Characterization of channel width dependence of gate delay in 0.18-μm CMOS technology

Verification of overlap and fringing capacitance models for MOSFETs

Optimization of implant anneals to improve transistor performance in a 0.15 μm CMOS technology

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