Optimization methods for post-bond die-internal/external testing in 3D stacked ICs

Noia, Brandon; Chakrabarty, Krishnendu; Marinissen, Erik Jan

doi:10.1109/test.2010.5699219

Cited by 60 publications

(18 citation statements)

References 22 publications

(38 reference statements)

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“…R M in the figure is the sum of R p , R i , R M p1on and R Mn1on . If a resistive open defect whose resistance is R f occurs at b, I Dt flows whose value is defined as an intersection P2 of the I Dt − V AK characteristic curve and the line defined by (8).…”

Section: Testability Of Open Defectsmentioning

confidence: 99%

A Design for Testability of Open Defects at Interconnects in 3D Stacked ICs

Ashikin

Hashizume

Yotsuyanagi

et al. 2018

IEICE Trans. Inf. & Syst.

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SUMMARY A design-for-testability method and an electrical interconnect test method are proposed to detect open defects occurring at interconnects among dies and input/output pins in 3D stacked ICs. As part of the design method, an nMOS and a diode are added to each input interconnect. The test method is based on measuring the quiescent current that is made to flow through an interconnect to be tested. The testability is examined both by SPICE simulation and by experimentation.

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Section: Testability Of Open Defectsmentioning

confidence: 99%

A Design for Testability of Open Defects at Interconnects in 3D Stacked ICs

Ashikin

Hashizume

Yotsuyanagi

et al. 2018

IEICE Trans. Inf. & Syst.

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“…Therefore, the partial stacks (mid-bond) and the complete stacks (post-bond) may need testing. A test architecture optimization technique for 3D-SIC is proposed in [Noia10a] to minimize the test application time for both mid-and post-bond test stages. It is demonstrated that an optimal DfT architecture considering these test stages is different compared with the situation that only the final test stage is considered [Noia10a].…”

Section: Related Work 29mentioning

confidence: 99%

Thermal Issues in Testing of Advanced Systems on Chip

Ghaleshahi¹

2015

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Many cutting-edge computer and electronic products are powered by advanced Systems-on-Chip (SoC). Advanced SoCs encompass superb performance together with large number of functions. This is achieved by efficient integration of huge number of transistors. Such very large scale integration is enabled by a core-based design paradigm as well as deepsubmicron and 3D-stacked-IC technologies. These technologies are susceptible to reliability and testing complications caused by thermal issues. Three crucial thermal issues related to temperature variations, temperature gradients, and temperature cycling are addressed in this thesis.Existing test scheduling techniques rely on temperature simulations to generate schedules that meet thermal constraints such as overheating prevention. The difference between the simulated temperatures and the actual temperatures is called temperature error. This error, for past technologies, is negligible. However, advanced SoCs experience large errors due to large process variations. Such large errors have costly consequences, such as overheating, and must be taken care of. This thesis presents an adaptive approach to generate test schedules that handle such temperature errors.Advanced SoCs manufactured as 3D-stacked-ICs experience large temperature gradients. Temperature gradients accelerate certain early-life defect mechanisms. These mechanisms can be accelerated using gradientbased, burn-in like operations so that the defects are detected before shipping. Moreover, temperature gradients exacerbate some delay-related defects. In order to detect such defects, testing must be performed when appropriate temperature-gradients are enforced. Schedule-based techniques that enforces the temperature-gradients for burn-in like operations and delay testing are proposed in this thesis. Abstract iiThe last thermal issue addressed by this thesis is related to temperature cycling. Temperature cycling test procedures are usually applied to safetycritical systems to detect cycling-related early-life failures. Such failures affect advanced SoCs, particularly through-silicon-via structures in 3D-stacked-ICs. An efficient schedule-based cycling-test technique that combines cycling acceleration with testing is proposed in this thesis. The proposed technique fits into existing 3D testing procedures and does not require temperature chambers. Therefore, the overall cycling acceleration and testing cost can be drastically reduced.All the proposed techniques have been implemented and evaluated with extensive experiments based on ITC'02 benchmarks as well as a number of 3D stacked ICs. Experiments show that the proposed techniques work effectively and reduce the test costs. We have also developed a fast temperature simulation technique based on a closed-form solution for the temperature equations. Experiments demonstrate that the proposed simulation technique reduces the test schedule generation time by more than half.iii Populärvetenskaplig sammanfattningMånga banbrytande dator-och elektronikprodukter drivs...

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“…Although interest in 3D-SIC testing has surged in the past year and a number of test and DFT solutions have been proposed [50,51,52,54,67,66], pre-bond TSV testing remains a major challenge. Recent efforts have identified some possible solutions to pre-bond TSV testing.…”

Section: Prior Work On Bist Techniques and Their Drawbacksmentioning

confidence: 99%

Design-for-Test and Test Optimization Techniques for TSV-based 3D Stacked ICs

Noia

Chakrabarty

2014

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As integrated circuits (ICs) continue to scale to smaller dimensions, long interconnects have become the dominant contributor to circuit delay and a significant component of power consumption. In order to reduce the length of these interconnects, 3D integration and 3D stacked ICs (3D SICs) are active areas of research in both academia and industry. 3DSICs not only have the potential to reduce average interconnect length and alleviate many of the problems caused by long global interconnects, but they can offer greater design flexibility over 2D ICs, significant reductions in power consumption and footprint in an era of mobile applications, increased on-chip data bandwidth through delay reduction, and improved heterogeneous integration.Compared to 2D ICs, the manufacture and test of 3D ICs is significantly more complex.Through-silicon vias (TSVs), which constitute the dense vertical interconnects in a die stack, are a source of additional and unique defects not seen before in ICs. At the same time, testing these TSVs, especially before die stacking, is recognized as a major challenge.The testing of a 3D stack is constrained by limited test access, test pin availability, power, and thermal constraints. Therefore, efficient and optimized test architectures are needed to ensure that pre-bond, partial, and complete stack testing are not prohibitively expensive.Methods of testing TSVs prior to bonding continue to be a difficult problem due to test access and testability issues. Although some built-in self-test (BIST) techniques have been proposed, these techniques have numerous drawbacks that render them impractical. In this dissertation, a low-cost test architecture is introduced to enable pre-bond TSV test through iv TSV probing. This has the benefit of not needing large analog test components on the die, which is a significant drawback of many BIST architectures. Coupled with an optimization method described in this dissertation to create parallel test groups for TSVs, test time for pre-bond TSV tests can be significantly reduced. The pre-bond probing methodology is expanded upon to allow for pre-bond scan test as well, to enable both pre-bond TSV and structural test to bring pre-bond known-good-die (KGD) test under a single test paradigm.The addition of boundary registers on functional TSV paths required for pre-bond probing results in an increase in delay on inter-die functional paths. This cost of test architecture insertion can be a significant drawback, especially considering that one benefit of 3D integration is that critical paths can be partitioned between dies to reduce their delay. This dissertation derives a retiming flow that is used to recover the additional delay added to TSV paths by test cell insertion.Reducing the cost of test for 3D-SICs is crucial considering that more tests are necessary during 3D-SIC manufacturing. To reduce test cost, the test architecture and test scheduling for the stack must be optimized to reduce test time across all necessary test insertions. This dissertation exam...

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Optimization methods for post-bond die-internal/external testing in 3D stacked ICs

Cited by 60 publications

References 22 publications

A Design for Testability of Open Defects at Interconnects in 3D Stacked ICs

A Design for Testability of Open Defects at Interconnects in 3D Stacked ICs

Thermal Issues in Testing of Advanced Systems on Chip

Design-for-Test and Test Optimization Techniques for TSV-based 3D Stacked ICs

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