Optimization design of high-speed data acquisition system based on DMA double cache mechanism

Zhou, Weina; Yang, Shuang

doi:10.1016/j.mejo.2022.105577

Cited by 6 publications

(2 citation statements)

References 8 publications

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“…At the end of each block calculation, A/B/C/D/E and H0 ∼ H4 are added to form the new H0 ∼ H4. 17,18 Then, each block is processed with four rounds of the main loop, with 20 calculations in each round, and the output of the previous round is used as input for the next round. Each computation does a non-linear function operation on B, C, and D in A/B/C/D/E.…”

Section: A Sha-1 Algorithm Modelmentioning

confidence: 99%

DMA controller design based on SHA-1 dual channel improvement algorithm

Wang,

He,

Shi

2023

AIP Advances

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In order to make direct memory access (DMA) high-speed transmission while ensuring the security and integrity of data, the traditional Secure Hash Algorithm (SHA) is improved from the algorithm model and hardware architecture level by adopting the methods of data synchronization preprocessing and multi-block multi-output, and a dual-channel design with instant data comparison and data error correction functions adapted to high-speed DMA is achieved. The simulation results show that the maximum clock frequency of the DMA controller is 120 MHz and the throughput rate is up to 3.8 Gbps. The improved comparison channel can output the message summary at an interval of 0.56 μs, whereas the traditional algorithm needs to wait five times as long as the data handling time. The error correction channel also implements multi-block output and error block indexing. The results show that the improved dual-channel design based on the SHA algorithm can be highly adapted to DMA controllers and has good application prospects.

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Section: A Sha-1 Algorithm Modelmentioning

confidence: 99%

DMA controller design based on SHA-1 dual channel improvement algorithm

Wang,

He,

Shi

2023

AIP Advances

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“…With the increasing volume of data in data-intensive technical fields such as meteorology, radar, and aerospace, there is a growing demand for storage subsystems that can handle large capacity and high bandwidth [1,2,3,4,5,6].The Non-Volatile Memory Express (NVMe) technology [7] is the preferred option due to its superior storage capabilities, speed, and compatibility, facilitated by its parallel, low-latency underlying media data channels that mimic high-performance processor architectures [8,9]. Additionally, the Field Programmable Gate Arrays (FPGA) is becoming increasingly popular in the front end of data acquisition as it provides high flexibility and reliability [10,11,12,13,14,15]. Therefore, the FPGA-based NVMe storage subsystem is recently a commonly used solution in data-intensive technical fields.…”

Section: Introductionmentioning

confidence: 99%

A high performance NVMe host logic engine based on dynamically configurable queues and co-design of NVMe and PCIe

Zhibin,

Yu,

et al. 2024

IEICE Electron. Express

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Aiming at the demand for FPGA-based high-bandwidth NVMe SSD host access, this letter presents an NVMe over PCIe Hardware Acceleration Engine (NoPHAE), which has two innovative aspects. Firstly, an NVMe Queues Engine is integrated into the NoPHAE to enhance I/O performance and reduce resource consumption. The NVMe Queues Engine provides dynamic queue configuration and introduces a virtual completion queue, which reduces resource consumption by 20%. Secondly, a PCIe Acceleration Engine is built in the NoPHAE, which implements the co-design of PCIe and NVMe and optimizes the timing for processing PCIe transport layer transactions, resulting in a significant increase in data throughput. Test results indicate that the sequential read and write speed of the NoPHAE is 7.93 times faster than that of the baseline, and the random read and write performance is two times faster than that of the baseline.

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A secure SoC architecture design with dual DMA controllers

Wang,

He,

Shi

2024

AIP Advances

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With the continuous advancement of System-on-Chip (SoC) technologies, the burgeoning data volumes emphasize the paramount importance of safeguarding data security and integrity. In this study, by leveraging Ascon in conjunction with enhancements to the SHA-1 algorithm, two secure Direct Memory Access (DMA) controllers are designed to facilitate data encryption and comparison, respectively, culminating in the proposal of an SoC architecture featuring dual DMA controllers. Simulation outcomes demonstrate the system’s ability to achieve a maximum clock frequency of 120 MHz, offering a throughput rate of up to 3.2 GB/s. The multi-master multi-slave AHB bus matrix within the system operates impeccably, ensuring smooth functionality. Furthermore, the two DMA controllers exhibit independent operation, featuring flexible start-stop capabilities. Notably, they operate harmoniously without conflicts, optimizing the area utilization while adhering to a low power consumption design methodology. The results unequivocally affirm the feasibility of designing a secure SoC integrated with two DMA controllers. This hardware-based approach effectively ensures data security, showcasing promising prospects for real-world applications.

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Optimization design of high-speed data acquisition system based on DMA double cache mechanism

Cited by 6 publications

References 8 publications

DMA controller design based on SHA-1 dual channel improvement algorithm

DMA controller design based on SHA-1 dual channel improvement algorithm

A high performance NVMe host logic engine based on dynamically configurable queues and co-design of NVMe and PCIe

A secure SoC architecture design with dual DMA controllers

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