DMA controller design based on SHA-1 dual channel improvement algorithm

Abstract

In order to make direct memory access (DMA) high-speed transmission while ensuring the security and integrity of data, the traditional Secure Hash Algorithm (SHA) is improved from the algorithm model and hardware architecture level by adopting the methods of data synchronization preprocessing and multi-block multi-output, and a dual-channel design with instant data comparison and data error correction functions adapted to high-speed DMA is achieved. The simulation results show that the maximum clock frequency of the DMA controller is 120 MHz and the throughput rate is up to 3.8 Gbps. The improved comparison channel can output the message summary at an interval of 0.56 μs, whereas the traditional algorithm needs to wait five times as long as the data handling time. The error correction channel also implements multi-block output and error block indexing. The results show that the improved dual-channel design based on the SHA algorithm can be highly adapted to DMA controllers and has good application prospects.