Optimization and realization of sub-100-nm channel length single halo p-MOSFETs

Abstract

Abstract-Single halo p-MOSFETs with channel lengths down to 100 nm are optimized, fabricated, and characterized as part of this study. We show extensive device characterization results to study the effect of large angle adjust implant parameters on device performance and hot carrier reliability. Results on both conventionally doped and single halo p-MOSFETs have been presented for comparison purposes.

All‐Printed Carbon Nanotube finFETs on Plastic Substrates for High‐Performance Flexible Electronics

“…FinFET18 is a type of transistor developed in silicon electronics with dielectric and gate wrapping around a silicon “fin” to have higher channel conduction while suppressing the short‐channel effect. At a 100 nm gate length, a traditional silicon‐based metal‐oxide–semiconductor FET (MOSFET) device19 has a transconductance of about 300 μS μm −1 at a drain voltage VD = 1.2 V while a double‐gate silicon finFET20 is reported to show a transconductance of 633 μS μm −1 , showing significant performance enhancement. Here, we describe a single‐step transfer printing method to directly print a novel dielectric‐wrapped CNT nanostructure similar to finFETs for high‐performance, flexible, all‐printed CNT transistors on a plastic substrate, which have demonstrated mobilities of 27 ± 10 cm 2 V −1 s −1 and on/off ratios of 10 2 –10 4 .…”

Degradation of 1/f noise in short channel MOSFETs due to halo angle induced VT non-uniformity and extra trap states at interface

“…were proposed [7][8][9] to get rid of these negative effects eliminating halo implants. The impact of halo angle on hot carrier reliability was also reported in literature [10,11]. Our recent study focused on low-frequency noise and the analysis showed that a larger halo angle resulted in degraded 1/f noise performance which should be one of the big concerns for analog and RF device design.…”

Optimization of Single Halo p-MOSFET Implant Parameters for Improved Analog Performance and Reliability

“…The devices used in this work are p-channel Conventional and Single Halo (SH) MOSFETs fabricated on the same wafer using bulk CMOS technology [2,3]. The channel implant (Arsenic) for conventional devices is carried out before the gate oxidation, while for the SH devices a channel implantation is done from source side after the gate stack formation.…”