Optimally Embedding 3-Ary n-Cubes into Grids

Fan, Weibei; Fan, Jianxi; Lin, Cheng-Kuan; Wang, Yan; Han, Yuejuan; Wang, Ruchuan

doi:10.1007/s11390-019-1893-0

Cited by 29 publications

(5 citation statements)

References 37 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…The wirelength of graph is used in many areas, including circuit layout, networking, and code design. Some researches on the wirelength of graphs have been studied …”

Section: Related Workmentioning

confidence: 99%

Reconfigurable Fault‐tolerance mapping of ternary N‐cubes onto chips

Fan

Han

et al. 2020

Concurrency and Computation

View full text Add to dashboard Cite

Network-on-chip (NoC) is a new design method of system-on-chip used in very large scale integrated circuit (VLSI) systems. It is an important issue for choosing the appropriate topology for NoC. Wirelength and layout area are significant parameters affecting NoC due to the restriction of chip area. In this paper, we propose a new interconnection network called the incomplete ternary n-cube for parallel computing systems. Then, a linear algorithm is proposed to layout incomplete ternary n-cube network onto torus NoC. Furthermore, the failure of interconnection network is also taken into account, and a fault-tolerant layout of incomplete ternary n-cube with faulty edges into torus NoC is verified. Theoretical analysis demonstrates that the proposed algorithm can reduce the network cost and wirelength, which be conducive to estimate the wire length and chip area. KEYWORDSfault tolerance, graph embedding, network-on-Chip, reconfigurable, wirelength INTRODUCTIONWith semiconductor technology entering the nanometer stage, it has become a reality for the integration of 100 billion transistors in a single chip. How to utilize a large number of transistors effectively is an important issue of the chip architecture. It has become very difficult to improve the overall performance of the system by improving the performance of the single processor core; the difficulty and complexity of chip design are also increasing. 1,2 Network-on-chip (NoC) has the advantages of high integration, low power consumption, low cost, and small volume, and it has become one of the mainstreams of very large scale integration (VLSI) system design. 3Network topology research is an important aspect of NoC. The network on chip uses the topological structure of computer network for reference. Ring-based and torus-based NoC architectures are illustrated in Figure 1 and Figure 2. Due to its own characteristics of NoC, such as a large number of available communication wire resources, a large amount of communication can be carried out between the cores, restricted by the area of the chip, and the layout of the regular network. 4,5 Therefore, NoC has certain special requirements for the topology structure.Due to the restriction of the chip area, the interconnection network and the total wire length become the crucial issues that affect the NoC communications. It is an auxiliary consideration for the cost of NoCs with respect to their interconnection networks.The more complex of networks, the higher in connectivity wiring and costs. Therefore, it is desirable to substitute a simple network for NoC with complex networks as an alternative. In such cases, one of the primary targets is improving network performance by providing better static topology features such as diameter and average distance between vertices. 6-8 Nevertheless, when designing network architecture, it is crucial to consider the influence of physical design constraints, for example wirelength, wiring congestion, and network cost. Li et al 9 studied that, in contrast to normal beliefs, NoCs suf...

show abstract

“…The wirelength of graph is used in many areas, including circuit layout, networking, and code design. Some researches on the wirelength of graphs have been studied …”

Section: Related Workmentioning

confidence: 99%

Reconfigurable Fault‐tolerance mapping of ternary N‐cubes onto chips

Fan

Han

et al. 2020

Concurrency and Computation

View full text Add to dashboard Cite

show abstract

“…Until then only approximations were given in the form of bounds 10,15,17 . Here are few works which are concerned about optimizing the layout for the considered embedding: complete Josephus cube into tree related architectures, 8 balanced complete multipartite graphs onto cartesian product between {Path, Cycle} and trees, 18 balanced complete multipartite graphs onto grids and tree related structures, 19 spined cube into grid, 20 complete bipartite graph into sibling tree, 21 augmented cube into tree related and windmill structures, 9 fault tolerance mapping of ternary

N

‐cube onto chips, 4 hierarchical cube into linear array and

k

‐rooted complete binary trees, 5 hierarchical folded cubes into linear arrays and complete binary trees, 1 circular layout of hypercube, 12 hypercube into certain trees, 6 locally twisted cube into grid, 13 familiar graphs onto hypercube, 7 hypercube into cylinder, 14 and 3‐Ary

n

‐cube into grid 22 …”

Section: Introductionmentioning

confidence: 99%

Optimization of layout for embedding half hypercube into conventional tree architectures

Immanuel,

Greeni

2024

Concurrency and Computation

View full text Add to dashboard Cite

SummaryEmbedding a graph into another graph can be utilized for structural simulation, processor allocation, and algorithm porting in the field of parallel architecture. This has the potential to enhance the physical layout of network‐on‐chip (NoC) devices as well as to investigate their virtualization possibilities. Layout is one of the many indicators of graph embedding. An optimal layout in NoC design can result in a decreased wiring area and cost, as well as the reduction in communication delay between parallel processing components. In this work, the guest graph is the half hypercube, which possess efficient routing, fault tolerance, and Hamiltonian features. The edge isoperimetric problems is solved for the half hypercube using a novel technique called the isochronal ordering. The host graphs considered in our work are complete binary trees, ‐rooted complete binary trees, and other few predominantly investigated tree based architectures.

show abstract

“…e minimum layout problem plays an important role in finding an optimal solution for very large-scale integration (VLSI) chips physical layout [2], minimizing time delay of simulations in parallel computer systems, computer aided designs, structural engineering, cloning and visual stimuli models, and parallel architecture [7,8]. e computation of layout measure has been already studied in a variety of papers, see [9,10] and the references cited therein, for more details. e present study continues the layout computation of circulant graphs into path-and cycle-of-complete graphs.…”

Section: Introductionmentioning

confidence: 99%

Characterization of the Congestion Lemma on Layout Computation

Liu

Shalini

Arockiaraj³

et al. 2021

Journal of Mathematics

View full text Add to dashboard Cite

An embedding of a guest network G N into a host network H N is to find a suitable bijective function between the vertices of the guest and the host such that each link of G N is stretched to a path in H N . The layout measure is attained by counting the length of paths in H N corresponding to the links in G N and with a complexity of finding the best possible function overall graph embedding. This measure can be computed by summing the minimum congestions on each link of H N , called the congestion lemma. In the current study, we discuss and characterize the congestion lemma by considering the regularity and optimality of the guest network. The exact values of the layout are generally hard to find and were known for very restricted combinations of guest and host networks. In this series, we derive the correct layout measures of circulant networks by embedding them into the path- and cycle-of-complete graphs.

show abstract

Optimally Embedding 3-Ary n-Cubes into Grids

Cited by 29 publications

References 37 publications

Reconfigurable Fault‐tolerance mapping of ternary N‐cubes onto chips

Reconfigurable Fault‐tolerance mapping of ternary N‐cubes onto chips

Optimization of layout for embedding half hypercube into conventional tree architectures

Characterization of the Congestion Lemma on Layout Computation

Contact Info

Product

Resources

About