Reconfigurable Fault‐tolerance mapping of ternary N‐cubes onto chips

Abstract

Network-on-chip (NoC) is a new design method of system-on-chip used in very large scale integrated circuit (VLSI) systems. It is an important issue for choosing the appropriate topology for NoC. Wirelength and layout area are significant parameters affecting NoC due to the restriction of chip area. In this paper, we propose a new interconnection network called the incomplete ternary n-cube for parallel computing systems. Then, a linear algorithm is proposed to layout incomplete ternary n-cube network onto torus NoC. Furthermore, the failure of interconnection network is also taken into account, and a fault-tolerant layout of incomplete ternary n-cube with faulty edges into torus NoC is verified. Theoretical analysis demonstrates that the proposed algorithm can reduce the network cost and wirelength, which be conducive to estimate the wire length and chip area. KEYWORDSfault tolerance, graph embedding, network-on-Chip, reconfigurable, wirelength INTRODUCTIONWith semiconductor technology entering the nanometer stage, it has become a reality for the integration of 100 billion transistors in a single chip. How to utilize a large number of transistors effectively is an important issue of the chip architecture. It has become very difficult to improve the overall performance of the system by improving the performance of the single processor core; the difficulty and complexity of chip design are also increasing. 1,2 Network-on-chip (NoC) has the advantages of high integration, low power consumption, low cost, and small volume, and it has become one of the mainstreams of very large scale integration (VLSI) system design. 3Network topology research is an important aspect of NoC. The network on chip uses the topological structure of computer network for reference. Ring-based and torus-based NoC architectures are illustrated in Figure 1 and Figure 2. Due to its own characteristics of NoC, such as a large number of available communication wire resources, a large amount of communication can be carried out between the cores, restricted by the area of the chip, and the layout of the regular network. 4,5 Therefore, NoC has certain special requirements for the topology structure.Due to the restriction of the chip area, the interconnection network and the total wire length become the crucial issues that affect the NoC communications. It is an auxiliary consideration for the cost of NoCs with respect to their interconnection networks.The more complex of networks, the higher in connectivity wiring and costs. Therefore, it is desirable to substitute a simple network for NoC with complex networks as an alternative. In such cases, one of the primary targets is improving network performance by providing better static topology features such as diameter and average distance between vertices. 6-8 Nevertheless, when designing network architecture, it is crucial to consider the influence of physical design constraints, for example wirelength, wiring congestion, and network cost. Li et al 9 studied that, in contrast to normal beliefs, NoCs suf...

Optimization of layout for embedding half hypercube into conventional tree architectures

“…These guest and host graphs usually are interconnection networks which enables task distribution, architectural modeling, and algorithm migration 1 . In recent decades, embedding has been investigated for different significant and architecturally vital interconnection networks 2–7 . Hypercubes and hypercube variants have attracted the most recognition and have been investigated extensively regarding embedding 2,8–14 .…”

“…Until then only approximations were given in the form of bounds 10,15,17 . Here are few works which are concerned about optimizing the layout for the considered embedding: complete Josephus cube into tree related architectures, 8 balanced complete multipartite graphs onto cartesian product between {Path, Cycle} and trees, 18 balanced complete multipartite graphs onto grids and tree related structures, 19 spined cube into grid, 20 complete bipartite graph into sibling tree, 21 augmented cube into tree related and windmill structures, 9 fault tolerance mapping of ternary $$$ N $$$‐cube onto chips, 4 hierarchical cube into linear array and $$$ k $$$‐rooted complete binary trees, 5 hierarchical folded cubes into linear arrays and complete binary trees, 1 circular layout of hypercube, 12 hypercube into certain trees, 6 locally twisted cube into grid, 13 familiar graphs onto hypercube, 7 hypercube into cylinder, 14 and 3‐Ary $$$ n $$$‐cube into grid 22 …”