Optimal wire ordering and spacing in low power semiconductor design

Abstract

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An Interconnect Bus Power Optimization Method

“…As self-capacitance and relation between self-capacitance and wire space are not considered simultaneously in Refs. [6,[9][10][11], we verify whether their conclusions still hold. The results indicate that conclusions in Refs.…”

An interconnecting bus power optimization method combining interconnect wire spacing with wire ordering

“…As these two factors were not considered in Refs. [10], [13]- [15], whether their conclusions still hold in this condition should be verified first. For the 8-bit interconnect bus with several distinct switching factor matrices in this paper, we search for the optimal wire order (including all possible wire orders) using different searching algorithms.…”

“…Abundant experimental data show that the conclusions in Refs. [10], [13]- [15] still hold in this paper on condition that the coupling capacitance is comparable to the self-capacitance while this requirement can be easily satisfied in nanometer scale integrated circuits.…”

“…Fortunately, the existence of a unique poweroptimal wire order has been proven in Refs. [10], [13]- [15]. Assuming that the coupling capacitance is inversely proportional to wire space and ignoring the self-capacitance, Zuber et al [10] and Gritzmann et al [13] presented and proved this specific wire order separately.…”

“…[10], [13]- [15]. Assuming that the coupling capacitance is inversely proportional to wire space and ignoring the self-capacitance, Zuber et al [10] and Gritzmann et al [13] presented and proved this specific wire order separately. Taking the same assumption and ignoring the relation between self-capacitance and wire space, Moiseev et al [14,15] also constructed and proved this optimal wire order.…”