Optimal Symbiosis and Fair Scheduling in Shared Cache

Hu, Xiameng; Wang, Xiaolin; Li, Yechen; Luo, Yingwei; Ding, Chen; Wang, Zhenlin

doi:10.1109/tpds.2016.2611572

Cited by 7 publications

(4 citation statements)

References 34 publications

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“…Cache partitioning has been studied to allocate caches between multiple processes to minimize the miss rate and maximize throughput [56], [57], to guarantee the fairness between applications [58], [59], [56], [60], [61], [62], [63], and to protect the latency-sensitive jobs from batch jobs [64], [65], [66], [67]. Constructing miss rate curves or utility curves can give users a hint to allocate fast memory between multiple workloads [57], [68], [69], [70], [71], [72]. If users already know the utility curves of workloads, an auction can be used to allocate fast memory between workloads [73], [74].…”

Section: Discussionmentioning

confidence: 99%

Adaptive Page Migration Policy With Huge Pages in Tiered Memory Systems

Heo

Wang

Cui

et al. 2022

IEEE Trans. Comput.

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Section: Discussionmentioning

confidence: 99%

Adaptive Page Migration Policy With Huge Pages in Tiered Memory Systems

Heo

Wang

Cui

et al. 2022

IEEE Trans. Comput.

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“…They may be categorized by sample selection and mechanism. Samples may be selected by addresses [5], accesses [20,26], or windows [25,46]. The sampling may be done using compiler support [5] or binary instrumentation [25,46].…”

Section: Related Workmentioning

confidence: 99%

“…Samples may be selected by addresses [5], accesses [20,26], or windows [25,46]. The sampling may be done using compiler support [5] or binary instrumentation [25,46]. Trace analysis precisely identifies reuses at block granularity, but it requires a program input to run, and its cost is proportional to the trace length.…”

Section: Related Workmentioning

confidence: 99%

Locality analysis through static parallel sampling

et al. 2018

Self Cite

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Locality analysis is important since accessing memory is much slower than computing. Compile-time locality analysis can provide detailed program-level feedback for compilers or runtime systems faster than trace-based locality analysis. In this paper, we describe a new approach to locality analysis based on static parallel sampling. A compiler analyzes loop-based code and generates sampler code which is run to measure locality. Our approach can predict precise cache line granularity miss ratio curves for complex loops with non-linear array references and even branches. The precision and overhead of static sampling are evaluated using PolyBench and a bit-reversal loop. Our result shows that by randomly sampling 2% of loop iterations, a compiler can construct almost exact miss ratio curves as trace based analysis. Sampling 0.5% and 1% iterations can achieve good precision and efficiency with an average 0.6% to 1% the time of tracing respectively. Our analysis can also be parallelized. The analysis may assist program optimization techniques such as tiling, program co-location, cache hint selection and help to analyze write locality and parallel locality.

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“…Contention on shared resources such as the last level cache (LLC) and memory bandwidth may cause serious performance degradation and unfairness, which makes efficient source allocation a critical issue in data centers. A number of methods have been proposed to address LLC contention in real systems in order to improve system throughput [8,36,37] or mitigate unfairness [8,14,29,37]. In the recent decade, memory bandwidth scheduling has been extensively studied using simulation [7, 12, 13, 15-17, 21, 24, 25, 28, 43].…”

Section: Introductionmentioning

confidence: 99%

Emba

Xiang

Wang

et al. 2019

Proceedings of the 48th International Conference on Parallel Processing

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On multi-core processors, contention on shared resources such as the last level cache (LLC) and memory bandwidth may cause serious performance degradation, which makes efficient resource allocation a critical issue in data centers. Intel recently introduces Memory Bandwidth Allocation (MBA) technology on its Xeon scalable processors, which makes it possible to allocate memory bandwidth in a real system. However, how to make the most of MBA to improve system performance remains an open question. In this work, (1) we formulate a quantitative relationship between a program's performance and its LLC occupancy and memory request rate on commodity processors. (2) Guided by the performance formula, we propose a heuristic bound-aware throttling algorithm to improve system performance and (3) we further develop a hierarchical clustering method to improve the algorithm's efficiency. (4) We implement these algorithms in EMBA, a low-overhead dynamic memory bandwidth scheduling system to improve performance on Intel commodity processors. The results show that, when multiple programs run simultaneously on a multi-core processor whose memory bandwidth is saturated, the programs with high memory bandwidth demand usually use bandwidth inefficiently compared with programs with medium memory bandwidth demand from the perspective of CPU performance. By slightly throttling the former's bandwidth, we can significantly improve the performance of the latter. On average, we improve system performance by 36.9% at the expense of 8.6% bandwidth utilization rate.

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Optimal Symbiosis and Fair Scheduling in Shared Cache

Cited by 7 publications

References 34 publications

Adaptive Page Migration Policy With Huge Pages in Tiered Memory Systems

Adaptive Page Migration Policy With Huge Pages in Tiered Memory Systems

Locality analysis through static parallel sampling

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