Optimal Lattice-Reduction Aided Successive Interference Cancellation for MIMO Systems

Lee, K. Kyungchun; Chun, Joohwan; Hanzo, Lajos

doi:10.1109/twc.2007.06058

Cited by 32 publications

(19 citation statements)

References 15 publications

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“…The MIMO detector is based on the minimum mean square error-successive interference cancellation (MMSE-SIC) detection algorithm [27]. In particular, latency is one of the critical factors that decides the overall system performance in an SIC receiver [28].…”

Section: Discussionmentioning

confidence: 99%

Efficient Implementation of a Pseudorandom Sequence Generator for High-Speed Data Communications

Hwang¹

2010

ETRI J

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A conventional pseudorandom sequence generator creates only 1 bit of data per clock cycle. Therefore, it may cause a delay in data communications. In this paper, we propose an efficient implementation method for a pseudorandom sequence generator with parallel outputs. By virtue of the simple matrix multiplications, we derive a well-organized recursive formula and realize a pseudorandom sequence generator with multiple outputs. Experimental results show that, although the total area of the proposed scheme is 3% to 13% larger than that of the existing scheme, our parallel architecture improves the throughput by 2, 4, and 6 times compared with the existing scheme based on a single output. In addition, we apply our approach to a 2×2 multiple input/multiple output (MIMO) detector targeting the 3rd Generation Partnership Project Long Term Evolution (3GPP LTE) system. Therefore, the throughput of the MIMO detector is significantly enhanced by parallel processing of data communications.Keywords: pseudorandom sequence generator, linear feedback shift register, matrix multiplication, 3GPP LTE system, MIMO detector. Manuscript received Sept. 4, 2009; revised Dec. 17, 2009; accepted Jan. 4, 2010. This work was supported by the IT R&D program of MKE/KEIT, Rep. of Korea [2006-S-001-04 I. IntroductionPseudorandom sequences [1] have been widely used in various fields, including communications, navigation, radar technology, cipher technologies, remote control, measurements, and industrial automation [2]. For example, pseudorandom sequences have been used in error-correcting codes [3], spread spectrum communication [4], [5], and system identification and parameter measurements [6], [7]. Other example applications are found in surface characterization and 3D scene modeling [8]. The design of a general purpose pseudorandom sequence generator has matured and has already been commercialized [9]-[11].Pseudorandom sequences are series of 1's and 0's that lack any definite pattern and look statistically independent and uniformly distributed. The sequences are deterministic, but exhibit noise properties similar to randomness [12]. In particular, a pseudorandom sequence generator is usually made up of shift registers with feedback. By linearly combining elements from taps of the shift register and feeding them back to the input of the generator, we can obtain a sequence of much longer repeat length using the same number of delay elements in the shift register. Therefore, these blocks are also referred to as a linear feedback shift register (LFSR) [13], [14]. The length of the shift register, the number of taps, and their positions in the LFSR are important to generate pseudorandom sequences with desirable auto-correlation properties [15]. However, the output of the conventional pseudorandom sequence generator is limited to 1 bit per clock cycle. This restriction can be a bottleneck for data communications and may cause a delay. have been proposed [16], [17]. The approaches describe a parallel architecture implementation of a pseudorandom...

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Section: Discussionmentioning

confidence: 99%

Efficient Implementation of a Pseudorandom Sequence Generator for High-Speed Data Communications

Hwang¹

2010

ETRI J

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“…In [2], the optimal LR-OSIC has been proposed by updating the mean and variance of the estimated symbolsṽ in the LR domain at each SIC stage.…”

Section: Ordering the Real Lattice Basis Of Channel Matrixmentioning

confidence: 99%

“…In this paper, we first apply the LR-OSIC, which is described in [2]. In the LR-OSIC, the estimated symbol is quantized using the rounding operation.…”

Section: Introductionmentioning

confidence: 99%

Low complexity MIMO detection using OSIC with conditional list generation

2013

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This paper proposes a low complexity MIMO detection using ordering SIC (OSIC) with conditional list generation. Combined with lattice-reduction (LR) technique, OSIC further gains the BER performance compared to SIC, since the more reliable signal is prior to being detected. However OSIC based on LR (LR-OSIC) has inferior performance to the maximum likelihood (ML) detection in large size MIMO systems. In this paper, we investigate the mean square error in LR domain to evaluate the condition of the channel. The proposed detection applies the conditional list detection to update the estimate of the LR-OSIC. The simulation results exhibited that the proposed detection achieved near-ML performance in the 8×8 MIMO and required almost same complexity of the LR-OSIC in the high E b /N 0 region.

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“…(3) MIMO based OFDM with soft-output SIC (Successive Interference Cancelation) like MIMO detection methods, preprocessing may apply [6]. Note that list based MIMO detection will result in another generic form.…”

Section: Soft-output Demappingmentioning

confidence: 99%

Instruction set support and algorithm-architecture for fully parallel multi-standard soft-output demapping on baseband processors

Amin

Appeltans

et al. 2010

2010 IEEE Workshop on Signal Processing Systems

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Soft output demapping is crucial for emerging standards with Turbo or LDPC FEC schemes. Existing soft output demapping techniques [9][4][5] [2] incur several problems when implementing on state of the art baseband processors:(1) too many operations, the number of average operation per-bit is even higher than that of FFTs; (2) difficult to exploit the potential parallelism supported by baseband processors;(3) difficult to support the wide variety of modulation schemes in a flexible way. In our work we take an instruction set centric approach to tackle the challenge. First, the instruction set requirement is defined to support fully parallel and flexible soft demapping. Then the requirement is propagated to guide algorithm and micro-architecture codesign to implement the required functionality. We have studied theoretical potential and detailed implementations on state of the art baseband processors. On an ADRES architecture slightly evolved from [3], the proposed scheme improves the number of instructions by 20.4 ×, improves the number of cycles by 21.9 ×, and improves the number of memory operations by 5.9 ×.

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Optimal Lattice-Reduction Aided Successive Interference Cancellation for MIMO Systems

Cited by 32 publications

References 15 publications

Efficient Implementation of a Pseudorandom Sequence Generator for High-Speed Data Communications

Efficient Implementation of a Pseudorandom Sequence Generator for High-Speed Data Communications

Low complexity MIMO detection using OSIC with conditional list generation

Instruction set support and algorithm-architecture for fully parallel multi-standard soft-output demapping on baseband processors

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