Instruction set support and algorithm-architecture for fully parallel multi-standard soft-output demapping on baseband processors

Abstract

Soft output demapping is crucial for emerging standards with Turbo or LDPC FEC schemes. Existing soft output demapping techniques [9][4][5] [2] incur several problems when implementing on state of the art baseband processors:(1) too many operations, the number of average operation per-bit is even higher than that of FFTs; (2) difficult to exploit the potential parallelism supported by baseband processors;(3) difficult to support the wide variety of modulation schemes in a flexible way. In our work we take an instruction set centric approach to tackle the challenge. First, the instruction set requirement is defined to support fully parallel and flexible soft demapping. Then the requirement is propagated to guide algorithm and micro-architecture codesign to implement the required functionality. We have studied theoretical potential and detailed implementations on state of the art baseband processors. On an ADRES architecture slightly evolved from [3], the proposed scheme improves the number of instructions by 20.4 ×, improves the number of cycles by 21.9 ×, and improves the number of memory operations by 5.9 ×.