Optimal Design Methods to Transform 3D NAND Flash into a High-Density, High-Bandwidth and Low-Power Nonvolatile Computing in Memory (nvCIM) Accelerator for Deep-Learning Neural Networks (DNN)

Lue, Hang-Ting; Hsu, Po-Kai; Wei, Ming‐Liang; Yeh, Teng-Hao; Du, Pei-Ying; Chen, Wei‐Chen; Wang, Keh-Chung; Lu, Chih‐Yuan

doi:10.1109/iedm19573.2019.8993652

Cited by 51 publications

(27 citation statements)

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“…A design scheme of synaptic architecture using NAND flash memory for performing MAC with multi-bit weight and multibit input has been proposed in Lue et al (2019). In this FIGURE 12 | Effect of stuck-at-off device ratio on simulated classification accuracy of QNN for (A) CIFAR 10 and (B) MNIST images.…”

Section: Comparison With Prior Workmentioning

confidence: 99%

“…In this FIGURE 12 | Effect of stuck-at-off device ratio on simulated classification accuracy of QNN for (A) CIFAR 10 and (B) MNIST images. scheme, lots of binary cells and BLs are utilized to represent a multilevel weight and a multilevel input, respectively, resulting in a substantial disadvantage in terms of synapse density (Lue et al, 2019). Furthermore, "shifter and adder" design is utilized to generate multilevel MAC, resulting in lots of burden in peripheral circuits (Lue et al, 2019).…”

Section: Comparison With Prior Workmentioning

confidence: 99%

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Neuromorphic Computing Using NAND Flash Memory Architecture With Pulse Width Modulation Scheme

Lee

2020

Front. Neurosci.

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A novel operation scheme is proposed for high-density and highly robust neuromorphic computing based on NAND flash memory architecture. Analog input is represented with time-encoded input pulse by pulse width modulation (PWM) circuit, and 4-bit synaptic weight is represented with adjustable conductance of NAND cells. Pulse width modulation scheme for analog input value and proposed operation scheme is suitably applicable to the conventional NAND flash architecture to implement a neuromorphic system without additional change of memory architecture. Saturated current-voltage characteristic of NAND cells eliminates the effect of serial resistance of adjacent cells where a pass bias is applied in a synaptic string and IR drop of metal wire resistance. Multiply-accumulate (MAC) operation of 4-bit weight and width-modulated input can be performed in a single input step without additional logic operation. Furthermore, the effect of quantization training (QT) on the classification accuracy is investigated compared with post-training quantization (PTQ) with 4-bit weight. Lastly, a sufficiently low current variance of NAND cells obtained by the read-verify-write (RVW) scheme achieves satisfying accuracies of 98.14 and 89.6% for the MNIST and CIFAR10 images, respectively.

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Section: Comparison With Prior Workmentioning

confidence: 99%

Section: Comparison With Prior Workmentioning

confidence: 99%

Neuromorphic Computing Using NAND Flash Memory Architecture With Pulse Width Modulation Scheme

Lee

2020

Front. Neurosci.

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“…While a synaptic architecture capable of a digital XNOR computation has been reported in [37], this work proposes a synaptic architecture that performs VMM in an analog fashion, greatly reducing the burden on peripheral circuits and energy consumption compared to a digital computation. A design scheme for performing VMM in NAND flash memory with a multi-bit weight has been reported in [38]. However, there has been a considerable disadvantage in cell density, because many single-level cells are used to represent a multi-bit weight [38].…”

Section: A Comparison With Previous Workmentioning

confidence: 99%

“…A design scheme for performing VMM in NAND flash memory with a multi-bit weight has been reported in [38]. However, there has been a considerable disadvantage in cell density, because many single-level cells are used to represent a multi-bit weight [38]. In addition, a "shifter and adder" design is used to produce multi-bit VMM, which imposes lots of burden on the peripheral circuits [38].…”

Section: A Comparison With Previous Workmentioning

confidence: 99%

“…However, there has been a considerable disadvantage in cell density, because many single-level cells are used to represent a multi-bit weight [38]. In addition, a "shifter and adder" design is used to produce multi-bit VMM, which imposes lots of burden on the peripheral circuits [38]. On the other hand, our scheme eliminates waste of cell density because one synapse consists of only two NAND cells with 8 conductance levels (3-bit).…”

Section: A Comparison With Previous Workmentioning

confidence: 99%

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NAND Flash Based Novel Synaptic Architecture for Highly Robust and High-Density Quantized Neural Networks With Binary Neuron Activation of (1, 0)

et al. 2020

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We propose a novel synaptic architecture based on a NAND flash memory for highly robust and high-density quantized neural networks (QNN) with 4-bit weight and binary neuron activation, for the first time. The proposed synaptic architecture is fully compatible with the conventional NAND flash memory architecture by adopting a differential sensing scheme and a binary neuron activation of (1, 0). A binary neuron enables using a 1-bit sense amplifier, which significantly reduces the burden of peripheral circuits and power consumption and enables bitwise communication between the layers of neural networks. Operating NAND cells in the saturation region eliminates the effect of metal wire resistance and serial resistance of the NAND cells. With a read-verify-write (RVW) scheme, low-variance conductance distribution is demonstrated for 8 levels. Vector-matrix multiplication (VMM) of a 4-bit weight and binary activation can be accomplished by only one input pulse, eliminating the need of a multiplier and an additional logic operation. In addition, quantization training can minimize the degradation of the inference accuracy compared to post-training quantization. Finally, the low-variance conductance distribution of the NAND cells achieves a higher inference accuracy compared to that of resistive random access memory (RRAM) devices by 2~7 % and 0.04~0.23 % for CIFAR 10 and MNIST datasets, respectively. INDEX TERMS NAND flash, neuromorphic, synaptic device, hardware neural network, in-memory computing, quantized neural networks, deep neural network

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Lateral Migration‐based Flash‐like Synaptic Device for Hybrid Off‐chip/On‐chip Training

Park,

Hwang,

Lee

et al. 2024

Adv Elect Materials

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An increase in the demand for artificial intelligence is leading to advanced research in the field of neuromorphic systems, which imitate human brain functions with the hope of increasing computational speed and lowering power consumption. Especially, the development of energy‐efficient and reliable synaptic devices is critical as synapses are fundamental building blocks of neuromorphic systems. In this study, by adjusting the charge injection pathway of conventional flash memory devices, a lateral migration‐based synaptic device is proposed. Using the efficient program/erase method, the proposed device is operable at a significantly low voltage while maintaining formidable retention and endurance characteristics. Furthermore, an efficient hybrid off‐chip/on‐chip training method using the proposed device is presented. The results demonstrate a variation‐robust neuromorphic system, indicating the superiority of the proposed device.

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Optimal Design Methods to Transform 3D NAND Flash into a High-Density, High-Bandwidth and Low-Power Nonvolatile Computing in Memory (nvCIM) Accelerator for Deep-Learning Neural Networks (DNN)

Cited by 51 publications

References 0 publications

Neuromorphic Computing Using NAND Flash Memory Architecture With Pulse Width Modulation Scheme

Neuromorphic Computing Using NAND Flash Memory Architecture With Pulse Width Modulation Scheme

NAND Flash Based Novel Synaptic Architecture for Highly Robust and High-Density Quantized Neural Networks With Binary Neuron Activation of (1, 0)

Lateral Migration‐based Flash‐like Synaptic Device for Hybrid Off‐chip/On‐chip Training

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