Optimal Body Biasing for Minimum Leakage Power in Standby Mode

Kim, Kyung Ki; Kim, Yong-Bin

doi:10.1109/iscas.2007.378256

Cited by 12 publications

(7 citation statements)

References 4 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Moreover, the requirement of low power relies on supply voltage scaling, making voltage variations a significant challenge. The quest for increase in higher operating frequencies has resulted in significantly high junction temperature and within-die temperature variation [10,16]. Therefore, the possible performance degradation due to PVT variations has become a major criterion in assessing the performance of a new technology.…”

Section: Pvt Variationsmentioning

confidence: 99%

“…Circuits with an excessive power dissipation are more susceptible to run-time failures and account for serious re-liability problems [10,16]. Figures 12 and 13 show that the PDP of the MOSFET gates increases with temperature; however, the PDP of the CNT-FET logic gates is constant.…”

Section: Temperature Variationmentioning

confidence: 99%

“…For example, a SRAM cell with (16, 0) PCNTFETs and (19, 0) NCNTFETs is represented by the index triplet (16,19,0). The difference in chirality between N-type and P-type CNTFETs must also take into account the performance of the SRAM memory cell.…”

Section: Dual-chirality Sram Cell Designmentioning

confidence: 99%

“…To investigate the SNM of the proposed dual-diameter CNT-FET SRAM, extensive simulations have been performed on CNTFET SRAM cells with index triplets of (10,19,0), (13,19,0), (16,19,0), (19,19,0), and (22,19,0) for the transistors. Figure 22 shows the simulation results of the read SNM of the SRAM cell at 0.9 V power supply and room temperature.…”

Section: Dual-chirality Sram Cell Designmentioning

confidence: 99%

See 3 more Smart Citations

Integrated Circuit Design Based on Carbon Nanotube Field Effect Transistor

Kim¹

2011

Transactions on Electrical and Electronic Materials

Self Cite

View full text Add to dashboard Cite

As complementary metal-oxide semiconductor (CMOS) continues to scale down deeper into the nanoscale, various device non-idealities cause the I-V characteristics to be substantially different from well-tempered metal-oxide semiconductor field-effect transistors (MOSFETs). The last few years witnessed a dramatic increase in nanotechnology research, especially the nanoelectronics. These technologies vary in their maturity. Carbon nanotubes (CNTs) are at the forefront of these new materials because of the unique mechanical and electronic properties. CNTFET is the most promising technology to extend or complement traditional silicon technology due to three reasons: first, the operation principle and the device structure are similar to CMOS devices and it is possible to reuse the established CMOS design infrastructure. Second, it is also possible to reuse CMOS fabrication process. And the most important reason is that CNTFET has the best experimentally demonstrated device current carrying ability to date. This paper discusses and reviewsthe feasibility of the CNTFET's application at this point of time in integrated circuits design by investigating different types of circuit blocks considering the advantages that the CNTFETs offer.

show abstract

Section: Pvt Variationsmentioning

confidence: 99%

Section: Temperature Variationmentioning

confidence: 99%

Section: Dual-chirality Sram Cell Designmentioning

confidence: 99%

Section: Dual-chirality Sram Cell Designmentioning

confidence: 99%

See 2 more Smart Citations

Integrated Circuit Design Based on Carbon Nanotube Field Effect Transistor

Kim¹

2011

Transactions on Electrical and Electronic Materials

Self Cite

View full text Add to dashboard Cite

show abstract

“…Their solution cannot dynamically control the FBB voltage, while the generated FBB voltage is highly sensitive to V DD and strongly temperature dependent. Other publications imply using a FBB generator without discussing in detail its implementation [7][8][9].…”

Section: A Forward Body Bias Generator For Digital Cmos Circuits Withmentioning

confidence: 99%

A forward body bias generator for digital CMOS circuits with supply voltage scaling

Meijer

Gyvez

Kup

et al. 2010

Proceedings of 2010 IEEE International Symposium on Circuits and Systems

View full text Add to dashboard Cite

Meijer, R.I.M.P.; Pineda de Gyvez, J.; Kup, B.; Uden, van, B.; Bastiaansen, P.; Lammers, M.; Vertregt, M. Document VersionPublisher's PDF, also known as Version of Record (includes final page, issue and volume numbers)Please check the document version of this publication:• A submitted manuscript is the author's version of the article upon submission and before peer-review. There can be important differences between the submitted version and the official published version of record. People interested in the research are advised to contact the author for the final version of the publication, or visit the DOI to the publisher's website.• The final author version and the galley proof are versions of the publication after peer review.• The final published version features the final layout of the paper including the volume, issue and page numbers. Link to publication General rightsCopyright and moral rights for the publications made accessible in the public portal are retained by the authors and/or other copyright owners and it is a condition of accessing publications that users recognise and abide by the legal requirements associated with these rights.• Users may download and print one copy of any publication from the public portal for the purpose of private study or research.• You may not further distribute the material or use it for any profit-making activity or commercial gain • You may freely distribute the URL identifying the publication in the public portal ? Take down policyIf you believe that this document breaches copyright please contact us providing details, and we will remove access to the work immediately and investigate your claim.

show abstract

Introduction

Levi

Fish

2020

Dual Mode Logic

View full text Add to dashboard Cite

Optimal Body Biasing for Minimum Leakage Power in Standby Mode

Cited by 12 publications

References 4 publications

Integrated Circuit Design Based on Carbon Nanotube Field Effect Transistor

Integrated Circuit Design Based on Carbon Nanotube Field Effect Transistor

A forward body bias generator for digital CMOS circuits with supply voltage scaling

Introduction

Contact Info

Product

Resources

About