Optimal and Near-optimal Global Register Allocation Using 0-1 Integer Programming

Goodwin, David W.; Wilken, Kent

doi:10.1002/(sici)1097-024x(199608)26:8<929::aid-spe40>3.0.co;2-t

Cited by 33 publications

(29 citation statements)

References 3 publications

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“…However, they fail considerably for irregular architectures which invariably come with a smaller number of registers. In the recent past, approaches for optimal register allocation [1,8,11] have been proposed. The register allocation problem is formulated as an integer linear program (ILP) and solved using a general purpose ILP solver [6].…”

Section: Related Workmentioning

confidence: 99%

“…The register allocation problem is formulated as an integer linear program (ILP) and solved using a general purpose ILP solver [6]. Although global register allocation is NP-complete, authors [8] have empirically demonstrated that it takes O(n 3 ) time to compute the optimal register allocation for real-life benchmarks. The runtime was reduced to O(n 1.3 ) when the problem was relaxed to compute near-optimal solutions [1].…”

Section: Related Workmentioning

confidence: 99%

“…7, 8 and 9, 10) are added to ensure a legal flow of liveness on merge and diverge nodes, respectively. More importantly, the constraints ensure an optimal spill code placement [8]. The following merge-node constraints are added for all the merge nodes.…”

Section: Attrib Spill = {Load St Ore}mentioning

confidence: 99%

See 2 more Smart Citations

Dynamic overlay of scratchpad memory for energy minimization

Verma

Wehmeyer

Marwedel

2004

Proceedings of the 2nd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis - CODES+ISSS

120

100

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The memory subsystem accounts for a significant portion of the aggregate energy budget of contemporary embedded systems. Moreover, there exists a large potential for optimizing the energy consumption of the memory subsystem. Consequently, novel memories as well as novel algorithms for their efficient utilization are being designed. Scratchpads are known to perform better than caches in terms of power, performance, area and predictability. However, unlike caches they depend upon software allocation techniques for their utilization. In this paper, we present an allocation technique which analyzes the application and inserts instructions to dynamically copy both code segments and variables onto the scratchpad at runtime. We demonstrate that the problem of dynamically overlaying scratchpad is an extension of the Global Register Allocation problem. The overlay problem is solved optimally using ILP formulation techniques. Our approach improves upon the only previously known allocation technique for statically allocating both variables and code segments onto the scratchpad. Experiments report an average reduction of 34% and 18% in the energy consumption and the runtime of the applications, respectively. A minimal increase in code size is also reported.

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Section: Related Workmentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

See 1 more Smart Citation

Dynamic overlay of scratchpad memory for energy minimization

Verma

Wehmeyer

Marwedel

2004

Proceedings of the 2nd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis - CODES+ISSS

120

100

View full text Add to dashboard Cite

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“…A number of models are built aiming at effectively assign variables into registers with less space and time complexity, while guaranteeing relatively higher code quality. These technical models involve: linear scan [19], integer linear programming [20], tree scan [21] and puzzle solving [33].…”

Section: Related Workmentioning

confidence: 99%

WCET-aware re-scheduling register allocation for real-time embedded systems with clustered VLIW architecture

Huang

Zhao

Xue

2012

Proceedings of the 13th ACM SIGPLAN/SIGBED International Conference on Languages, Compilers, Tools and Theory for Embedded Syst

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Worst-Case Execution Time (WCET) is one of the most important metrics in real-time embedded system design. For embedded systems with clustered VLIW architecture, register allocation, instruction scheduling, and cluster assignment are three key activities to pursue code optimization which have profound impact on WCET. At the same time, these three activities exhibit a phase ordering problem: Independently performing register allocation, scheduling and cluster assignment could have a negative effect on the other phases, thereby generating sub-optimal compiled codes. In this paper, a compiler level optimization, namely WCET-aware Re-scheduling Register Allocation (WRRA), is proposed to achieve WCET minimization for real-time embedded systems with clustered VLIW architecture. The novelty of the proposed approach is that the effects of register allocation, instruction scheduling and cluster assignment on the quality of generated code are taken into account for WCET minimization. These three compilation processes are integrated into a single phase to obtain a balanced result. The proposed technique is implemented in Trimaran 4.0. The experimental results show that the proposed technique can reduce WCET effectively, by 33% on average.

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“…Coalescing aims to eliminate copy instructions of program variables by assigning both variables the same machine register. What is common to graph coloring based approaches and most techniques [GW96,PS99,KG06] proposed is that both register allocation/spilling and coalescing are considered to be inherent sub-problems that are solved concurrently.…”

Section: Related Workmentioning

confidence: 99%

Progressive spill code placement

Ebner

Scholz

Krall

2009

Proceedings of the 2009 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems

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Register allocation has gained renewed attention in the recent past. Several authors propose a separation of the problem into decoupled sub-tasks including spilling, allocation, assignment, and coalescing. This approach is largely motivated by recent advances in SSA-based register allocation that suggest that a decomposition does not significantly degrade the overall allocation quality.The algorithmic challenges of intra-procedural spilling have been neglected so far and very crude heuristics were employed. In this work, (1) we introduce the constrained mincut (CMC) problem for solving the spilling problem, (2) we provide an integer linear program formulation for computing an optimal solution of CMC, and (3) we devise a progressive Lagrangian solver that is viable for production compilers. Our experiments with Spec2k and MiBench show that optimal solutions are feasible, even for very large programs, and that heuristics leave significant potential behind for small register files.

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Optimal and Near-optimal Global Register Allocation Using 0-1 Integer Programming

Cited by 33 publications

References 3 publications

Dynamic overlay of scratchpad memory for energy minimization

Dynamic overlay of scratchpad memory for energy minimization

WCET-aware re-scheduling register allocation for real-time embedded systems with clustered VLIW architecture

Progressive spill code placement

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