Dynamic overlay of scratchpad memory for energy minimization

Verma, Manish; Wehmeyer, Lars; Marwedel, Peter

doi:10.1145/1016720.1016748

Cited by 120 publications

(107 citation statements)

References 21 publications

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“…In addition, several works are based on dynamic profiling of the behavior of data [17], instructions [13] or both [35] to choose the scratchpad memory contents. These techniques are complementary to our strategy, which relies on the fact that garbage collection is a highly predictable virtual machine phase because its usage of methods is largely application independent.…”

Section: Related Workmentioning

confidence: 99%

Memory power optimization of Java-based embedded systems exploiting garbage collection information

Velasco

Atienza

Olcoz

2012

Journal of Systems Architecture

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a b s t r a c tNowadays, Java is used in all types of embedded devices. For these memory-constrained systems, the automatic dynamic memory manager (Garbage Collector or GC) has been always a key factor in terms of the Java Virtual Machine (JVM) performance. Moreover, in current embedded platforms, power consumption is becoming as important as performance. Thus, in this paper we present an exploration, from an energy viewpoint, of the different possibilities of memory hierarchies for high-performance embedded systems when used by state-of-the-art GCs. This is a starting point for a better understanding of the interactions between the Java applications, the memory hierarchy and the GC.Hence, we subsequently present two techniques to reduce energy consumption on Java-based embedded systems, based on exploiting GC information. The first technique uses GC execution behavior to reduce leakage energy consumption taking advantage of the low-power mode of actual multi-banked SDRAM memories and it is intended for generational collectors. This technique can achieve a reduction up to 50% of SDRAM memory leakage.The second technique involves the inclusion of a software-controlled (scratch-pad) memory that stores GC instructions under the JVM control to reduce the active energy consumption and also improve the performance of the target embedded system and it is aimed at all kind of garbage collectors. For this last technique we have experimented with two different approaches for selecting the GC code to be stored in the scratchpad memory: one static and one dynamic. Our experimental results show that the proposed dynamic scratchpad management approach for GCs enables up to 63% energy consumption reduction and 25% performance improvement during the collector phase, which means, in terms of JVM execution, a global reduction of 29% and 17% for energy and cycles, respectively.Overall, this work outlines that the key for an efficient low-power implementation of Java Virtual Machines for high-performance embedded systems is the synergy between the GC choice, the memory architecture tuning, and the inclusion of power management schemes controlled by the JVM, exploiting knowledge of the GC behavior.

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Section: Related Workmentioning

confidence: 99%

Memory power optimization of Java-based embedded systems exploiting garbage collection information

Velasco

Atienza

Olcoz

2012

Journal of Systems Architecture

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“…Among those considering data allocation for SPM, some have focussed on allocation strategies for affine programs only [2,5,6,8] while the rest have proposed more general solutions [7,10]. So far as we are aware, none of the existing strategies provide an integrated solution.…”

Section: Related Workmentioning

confidence: 99%

“…Towards bridging this gap, recent research has focussed on developing compiler-guided dynamic allocation strategies [6,7,10]. Such research holds out the potential of making SPM's more competitive with the performance of caches.…”

Section: Introductionmentioning

confidence: 99%

An integrated scratch-pad allocator for affine and non-affine code

Udayakumaran

Barua

2006

Proceedings of the Design Automation &Amp; Test in Europe Conference

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“…In this way, it ensures that as many accesses as possible can be executed in parallel. Some very recent approaches ( [36]) dynamically reallocate data in the local layer. At compile time they perform a life analysis of the task and insert instructionc to dynamically copy code segements and variables onto the scratchpad at runtime.…”

Section: Data Layout Based Techniquesmentioning

confidence: 99%

Power-efficient data management for dynamic applications

Marchal

Perez

Atienza

et al. 2006

System-on-Chip: Next Generation Electronics

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In recent years, the semiconductor industry has turned its focus towards heterogeneous multi-processor platforms. They are an economically viable solution for coping with the growing setup and manufacturing cost of silicon systems. Furthermore, their inherent flexibility also perfectly supports the emerging market of interactive, mobile data and content services. The platform's performance and energy depend largely on how well the data-dominated services are mapped on the memory subsystem. A crucial aspect thereby is how efficient data is transferred between the different memory layers. Several compilation techniques have been developed to optimally use the available bandwidth. Unfortunately, they do not take the interaction between multiple threads running on the different processors into account, only locally optimize the bandwidth nor deal with the dynamic behavior of these applications. The contributions of this chapter are to outline the main limitations of current techniques and to introduce an approach for dealing with the dynamic multi-threaded of our application domain. The design challenges of media-rich servicesBusiness analysts forecast a 250 billion dollar market for media-rich, mobile wireless terminals [53]. These systems require an enormous computational performance (40GOPS 1 ). Even though current PCs offer this performance requirement, they consume too much power (10-100W). Mobile devices should consume at least two or three orders of magnitude less power [30]. Furthermore, they should be cheap to successfully penetrate the consumer market. Consequently and in spite of the design issues, the engineering and manufacturing costs need to be reduced. Industry strongly believes that platforms are a potential way to meet the above challenges. The era of platform-based designA platform is a fixed micro-architecture together with a programming environment that minimizes mask-making costs and is flexible enough to work for a set of applications [4]. The production volumes can then remain high over an extended chip lifetime.Given the strong energy constraints, we must choose the flavor of these platforms. Since power is cubic to the processing frequency, parallelism is an effective to reduce power and energy consumption. Then, multiple simple processors are preferred to one complex speculative and out-of-order processor. In the right application domain, we can get better performance and spend less energy. Besides parallelism, heterogeneity is an alternative way to decrease the energy cost. For instance, the TI OMAP platform combines a RISC processor with a Digital Signal Processor (DSP). The RISC is more energy-efficient for the input/output processing and simple control-dominated 1 Giga Operations Per Second

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Dynamic overlay of scratchpad memory for energy minimization

Cited by 120 publications

References 21 publications

Memory power optimization of Java-based embedded systems exploiting garbage collection information

Memory power optimization of Java-based embedded systems exploiting garbage collection information

An integrated scratch-pad allocator for affine and non-affine code

Power-efficient data management for dynamic applications

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