Optimal and Near‐optimal Global Register Allocation Using 0-1 Integer Programming

Goodwin, David W.; Wilken, Kent

doi:10.1002/(sici)1097-024x(199608)26:8<929::aid-spe40>3.3.co;2-k

Cited by 35 publications

(19 citation statements)

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“…The method by Verma et al is motivated by the ILP formulation for global register allocation [34]. One other drawback of their approach is that like global register allocation methods, the solution though optimal is per procedure.…”

Section: Methods By Verma Et Al [87]mentioning

confidence: 99%

Compiler-decided dynamic memory allocation for scratch-pad based embedded systems

Udayakumaran

Barua

2003

Proceedings of the 2003 International Conference on Compilers, Architecture and Synthesis for Embedded Systems

141

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In this research we propose a highly predictable, low overhead and yet dynamic, memory allocation strategy for embedded systems with scratch-pad memory. A scratch-pad is a fast compiler-managed SRAM memory that replaces the hardwaremanaged cache. It is motivated by its better real-time guarantees vs cache and by its significantly lower overheads in energy consumption, area and overall runtime, even with a simple allocation scheme. Scratch-pad allocation methods primarily are of two types. First, softwarecaching schemes emulate the workings of a hardware cache in software. Instructions are inserted before each load/store to check the software-maintained cache tags.Such methods incur large overheads in runtime, code size, energy consumption and SRAM space for tags and deliver poor real-time guarantees, just like hardware caches. A second category of algorithms partitions variables at compile-time into the two banks. However, a drawback of such static allocation schemes is that they do not account for dynamic program behavior.We propose a dynamic allocation methodology for global and stack data and program code that (i) accounts for changing program requirements at runtime (ii) has no software-caching tags (iii) requires no run-time checks (iv) has extremely low overheads, and (v) yields 100% predictable memory access times. In this method data that is about to be accessed frequently is copied into the scratch-pad using compiler-inserted code at fixed and infrequent points in the program. Earlier data is evicted if necessary. When compared to an existing static allocation scheme, results show that our scheme reduces runtime by up to 39.8% and energy by up to 31.3% on average for our benchmarks, depending on the SRAM size used. The actual gain depends on the SRAM size, but our results show that close to the maximum benefit in run-time and energy is achieved for a substantial range of small SRAM sizes commonly found in embedded systems. Our comparison with a direct mapped cache shows that our method performs roughly as well as a cached architecture in runtime and energy while delivering better real-time benefits. Albert SchweitzerWith these thoughts in mind, I embark on this humble duty to acknowledge different people who have contributed to that light in their own ways.First and foremost, I acknowledge my parents, my brother and my sister-inlaw whose concern for my health and wellbeing, always drives me to work harder towards my goals.I would also like to acknowledge those who have helped me to complete this dissertation. My advisor, Dr. Rajeev Barua, has been an outstanding motivator.

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Section: Methods By Verma Et Al [87]mentioning

confidence: 99%

Compiler-decided dynamic memory allocation for scratch-pad based embedded systems

Udayakumaran

Barua

2003

Proceedings of the 2003 International Conference on Compilers, Architecture and Synthesis for Embedded Systems

141

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“…Their approach is motivated by the ILP formulation for global register allocation [Goodwin and Wilken 1996]. Both parts of the problem -finding what variables should be in the scratch-pad at different points in the program and what addresses they should be at -are solved using ILP formulations.…”

Section: Related Workmentioning

confidence: 99%

Dynamic allocation for scratch-pad memory using compile-time decisions

Udayakumaran

Domínguez

Barua

2006

ACM Trans. Embed. Comput. Syst.

183

156

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In this research we propose a highly predictable, low overhead and yet dynamic, memory allocation strategy for embedded systems with scratch-pad memory. A scratch-pad is a fast compiler-managed SRAM memory that replaces the hardware-managed cache. It is motivated by its better real-time guarantees vs cache and by its significantly lower overheads in energy consumption, area and overall runtime, even with a simple allocation scheme.Scratch-pad allocation primarily methods are of two types. First, software-caching schemes emulate the workings of a hardware cache in software. Instructions are inserted before each load/store to check the softwaremaintained cache tags. Such methods incur large overheads in runtime, code size, energy consumption and SRAM space for tags and deliver poor real-time guarantees just like hardware caches. A second category of algorithms partitions variables at compile-time into the two banks. However, a drawback of such static allocation schemes is that they do not account for dynamic program behavior. It is easy to see why a data allocation that never changes at runtime cannot achieve the full locality benefits of a cache.We propose a dynamic allocation methodology for global and stack data and program code that, (i) accounts for changing program requirements at runtime (ii) has no software-caching tags (iii) requires no run-time checks (iv) has extremely low overheads, and (v) yields 100% predictable memory access times. In this method data that is about to be accessed frequently is copied into the scratch-pad using compiler-inserted code at fixed and infrequent points in the program. Earlier data is evicted if necessary. When compared to a provably optimal static allocation, results show that our scheme reduces runtime by up to 39.8% and energy by up to 31.3% on average for our benchmarks, depending on the SRAM size used. The actual gain depends on the SRAM size, but our results show that close to the maximum benefit in run-time and energy is achieved for a substantial range of small SRAM sizes commonly found in embedded systems. Our comparison with a direct mapped cache shows that our method performs roughly as well as a cached architecture.

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“…Other research has cast the problem as set of constraints passed to an integer programming solver [22,23], or bin packing [86]. We focus on graph coloring in this work because it is the most common technique for optimizing compilers.…”

Section: Register Allocation and Spillingmentioning

confidence: 99%

Smart Register Files for High-Performance Microprocessors

Postiff

Mudge²

1999

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This report examines how the compiler can more efficiently use a large number of processor registers. The placement of data items into registers, called register allocation, is known to be one of the most important compiler optimizations for high-speed computers because registers are the fastest storage devices in the computer system. However, register allocation has been limited in scope because of aliasing in the memory system. To break this limitation and allow more data to be placed into registers, new compiler and microarchitecture support is needed.We propose the modification of register access semantics to include an indirect access mode. We call this optimization the Smart Register File. The smart register file allows the relaxation of overly-conservative assumptions in the compiler by having the hardware provide support for aliased data items in processor registers. As a result, the compiler can allocate data from a larger pool of candidates than in a conventional system. An attendant advantage is that the smart register file reduces the number of load and store operations executed by the processor. The simple addition of an indirect register access mode not only simplifies alias handling, but also provides opportunities for other optimizations. This dissertation examines several such optimizations. Report Documentation PageForm Public reporting burden for the collection of information is estimated to average 1 hour per response, including the time for reviewing instructions, searching existing data sources, gathering and maintaining the data needed, and completing and reviewing the collection of information. Send comments regarding this burden estimate or any other aspect of this collection of information, including suggestions for reducing this burden, to Washington Headquarters Services, Directorate for Information Operations and Reports, 1215 Jefferson Davis Highway, Suite 1204, Arlington VA 22202-4302. Respondents should be aware that notwithstanding any other provision of law, no person shall be subject to a penalty for failing to comply with a collection of information if it does not display a currently valid OMB control number.

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Optimal and Near‐optimal Global Register Allocation Using 0-1 Integer Programming

Cited by 35 publications

References 0 publications

Compiler-decided dynamic memory allocation for scratch-pad based embedded systems

Compiler-decided dynamic memory allocation for scratch-pad based embedded systems

Dynamic allocation for scratch-pad memory using compile-time decisions

Smart Register Files for High-Performance Microprocessors

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