Optimal and Heuristic Scheduling Algorithms for Asynchronous High-Level Synthesis

Andrikos, Nikos; Lavagno, Luciano

doi:10.1109/async.2011.18

Cited by 4 publications

(2 citation statements)

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“…For this decomposition style different techniques were proposed to the synthesis of data-paths and controllers [8][9][10][11][12][13][14][15][16]. Recently, there have been several attempts to demonstrate the potential advantages of the asynchronous circuits over its synchronous counterparts [17][18][19][20] and some asynchronous digital systems design methodologies have been developed successfully [5].…”

Section: João Luis V Oliveiramentioning

confidence: 99%

“…In the first one, the project involves asynchronous data-path, so does not present any delay, but the asynchronous data-path involves dual-rail components, presenting a very high cost [5,11]. In the second variant of "by decomposition" asynchronous circuits design, a delay is inserted in the project with synchronous data-path, defining the cycle time of the transition state [8][9][10][12][13][14][15][16].…”

Section: A Decomposition Style For Asynchronous Designmentioning

confidence: 99%

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Design of asynchronous systems on FPGA using direct mapping and synchronous specification

Oliveira

Bompean

Faria

et al. 2013

2013 International Conference on Reconfigurable Computing and FPGAs (ReConFig)

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Complex synchronous digital systems can be implemented on FPGAs (Field Programmable Gate Arrays), but due to the global clock, might have problems with clock skew, performance degradation and increased of power consumed. An alternative to these designs is the asynchronous paradigm that solves the problems related to the clock. However it is difficult to design asynchronous circuits, especially in the FPGA platform. This work presents in the style of asynchronous FSM (finite state machine) + data-path a method that implements asynchronous digital systems on FPGAs. The proposed method uses the tools of paradigm synchronous, thus synthesizes without the knowledge of asynchronous logic. Our method synthesizes the asynchronous FSM by direct mapping from the conventional state transition graph. Through a case study, it is shown the simplicity of the proposed methodology.

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