Optimal allocation of multiport memories in datapath synthesis

Abstract

OverviewMultiport memories can significantly reduce circuit complexity by allowing registers residing in the same memory t o share common d a t a paths between the memories and functional units. An earlier paper [1] described the advantages of using multiport memories in data path synthesis and provided a linear programming approach t o determine the maximum number of registers to place in a multiport memory with given port capabilit,ies However, t h a t paper considered allocation t o only one memory at a time and assumed the particular configuration of memories was totally prescribed by the designer.Here we extend that approach in various ways. We assign registers simultaneously t o a configuration of several memories; this gives a more uniform distribution of register activity across the memories and usually provides a more compact assignment, allowing even fewer ports and fewer module interconnections. We first extend the L.P. model and then present a fast heuristic approach that searches for an allocation. This allocation algorithm is part of a more general design tool that generates alternative multiport memory configurations and allows their rapid exploration. T h e designer specifies a range of design parameters and can control the thoroughness of the search. Within the limits set by the designer, the program finds the minimum cost configuration having a feasible register allocation. After describing the components of this system, we present some examples of its use. The Memory Allocation ProblemA memory configuration consists of a certain number of memories, each having a specific storage capacity and number of ports. T h e ports can have three functionalities: read-only; writeonly; and read/write. Given a particular memory configuration, the memory allocation problem consists finding some allocation of registers t o these memory modules that guarantees access on every control step t o all the registers participating in that control step..4llocating registers t o multiport memories is just one step in a sequence of steps t h a t converts a behavioral-level description of a circuit into a specification for the interconnection of functional units and storage elements. Clearly, detailed knowledge of register usage is needed in order t o determine which registers are active during the same control steps. Thus, register packing must follow the identification and minimization of registers, the association of prescribed operators with functional units, and the scheduling of operations in specific control steps. Data paths can be identified and routed only after the allocation of registers t o memories.Due t o often complex patterns of mutual register activity, a particular memory configuration may have no consistent packing, even if enough storage is available and enough ports appear t o be provided. On the other hand, any tw8.1 consistent allocation schemes are considered equivalent in terms of the packing problem. Although different register allocations tend to yield different module interconnection patterns,...

A scheduling algorithm for multiport memory minimization in datapath synthesis

“…al. [7] presented a heuristic algorithm in which registers are allocated to available multiport memories one-by-one. Due to the local nature of greedy search, the algorithm does not guarantee an optimal solution in the number of memory modules and the number of registers in each memory module.…”

A heuristic for data path synthesis using multiport memories

“…The comparison with Wilson e2 al. [25] is to demonstrate the quality of our proposed technique since it deals with multiport memories, where as the comparison to systems, which do not deal with multiport memories such as STAR [14], ADPS [29] and HAL [9], is to demonstrate that multiport memories can indeed significantly reduce the interconnection cost by using our proposed technique.…”

“…First example is a code sequence adopted from [25] as shown in Figure 5. By applying the technique discussed in this paper final synthesized data path for this example is given in Figure 6 and assignment of registers to memory ports is shown in Figure 7.…”

“…Their approach does not deal with the operation and connection allocation task. In the technique reported by Wilson et al [25] registers are allocated to multiport memories one-by-one, which is not necessarily an optimal solution. Wilson et al [26] presented an approach to find a minimal number of connections between memory ports and FU terminals.…”

A graph-theoretic approach for register file based synthesis

“…The architecture shown in Figure 6, was found by SOUPS. Table 2 shows the comparison of our architecture with that given by Ahmad k Chen, Wilson et al [9], and Sutarwala et al [8] …”