A heuristic for data path synthesis using multiport memories

Abstract

Recently there is a trend for the designer to group registers into register files for efficiently implementing large VLSl chips. Multiport memories provide an effective way for such an implementation. Interconnection minimization (such as multiplexers and tristate buffers) has become more difficult with the use of multiport memories. In this paper, a heuristic is presented which performs functional units and connection allocation tasks simulatneously to get better results for application specific designs assuming that registers have already been grouped to multiport memories. Experiments on benchmarks show very promising resu 1 ts.