Optical properties of bonded silicon silicide on insulator (S2OI): a new substrate for electronic and optical devices

Nayar, V.; Russell, J.; Carline, R. T.; Pidduck, A. J.; Quinn, C.; Nevin, Andy; Blackstone, S.

doi:10.1016/s0040-6090(97)00832-8

Cited by 12 publications

(5 citation statements)

References 2 publications

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“…Since we need a lower electron concentration in the collector region compared to what is required in the emitter region of the transistor, Aluminum (work function ϕ m,C = 4.28 eV) is used as the collector electrode buried between the silicon and BOX of the SOI. This buried aluminum electrode (as described in section IV) can be formed using wafer bonding techniques 8 9 10 11 12 13 . Although the Si film is intrinsic, we have assumed it to be un-intentionally doped with N D = 1 × 10 14 /cm 3 .…”

Section: Device Structure and Parametersmentioning

confidence: 99%

“…V-NPN BJT provided through a BiCMOS process has also been used for realizing a transducer design with large transconductance g m , low-noise and high linearity 7 for applications in RF and analog circuits. Recently, the series collector resistance of the bipolar transistors has been considerably reduced by incorporating a highly conducting buried silicide layer 8 9 10 11 between the top silicon layer and the buried oxide layer (BOX) of silicon-on-insulator substrates.…”

mentioning

confidence: 99%

“…A number of metal layers such as tungsten 8 9 10 , cobalt 12 , molybdenum 13 and others have been incorporated by bonding technology with low thermal budgets. However, in aggressively scaled devices, dopant fluctuation 14 15 and dopant activation 16 of the highly doped emitter and the base region of the BJT with high thermal budgets can be a bottleneck while integrating the bipolar process with the CMOS process on SOI incorporating a buried metal layer.…”

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confidence: 99%

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Vertical Bipolar Charge Plasma Transistor with Buried Metal Layer

Nadda

Kumar

2015

Sci Rep

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A self-aligned vertical Bipolar Charge Plasma Transistor (V-BCPT) with a buried metal layer between undoped silicon and buried oxide of the silicon-on-insulator substrate, is reported in this paper. Using two-dimensional device simulation, the electrical performance of the proposed device is evaluated in detail. Our simulation results demonstrate that the V-BCPT not only has very high current gain but also exhibits high BVCEO · fT product making it highly suitable for mixed signal high speed circuits. The proposed device structure is also suitable for realizing doping-less bipolar charge plasma transistor using compound semiconductors such as GaAs, SiC with low thermal budgets. The device is also immune to non-ideal current crowding effects cropping up at high current densities.

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Section: Device Structure and Parametersmentioning

confidence: 99%

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confidence: 99%

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confidence: 99%

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Vertical Bipolar Charge Plasma Transistor with Buried Metal Layer

Nadda

Kumar

2015

Sci Rep

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“…High melting point silicides are more stable against Si and, in addition, they allow self-aligned processing and have low electrical resistivities. Tungsten silicide has been successfully bonded to fabricate silicon-on-metal-on-insulator (SMOI) structures [2][3][4][5]. However, self-aligned silicidation of tungsten is very difficult.…”

Section: Introductionmentioning

confidence: 99%

Thermal stability of CoSi₂layers implemented in a silicon-on-insulator substrate

Zhao

Bay

Zimmermann

et al. 2006

Semicond. Sci. Technol.

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A silicon-on-metal-on-insulator substrate, consisting of a top Si layer, a buried CoSi 2 layer and a buried SiO 2 layer on a Si (1 0 0) substrate was formed using Co silicidation, wafer bonding and wafer splitting. It is shown that the buried silicide layers in this structure exhibit a much higher thermal stability than surface layers. Resistivity measurements and cross-sectional transmission electron microscopy investigations revealed that buried CoSi 2 layers withstand furnace anneals at 1000 • C up to 2 h, while surface CoSi 2 layers started to degrade after 10 min anneals at 1000 • C. The proposed substrate is most useful for BiCMOS applications.

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“…There have been many reports about the fabrication of a metallic silicide embedded in SOI [3][4][5][6][7]; but all of them use silicon direct wafer bonding with the grind/polish back (BESOI) method. In this work, a flexible Smart-cut ® technique is employed.…”

Section: Introductionmentioning

confidence: 99%

Buried tungsten silicide layer in silicon on insulator substrate by Smart-Cut®

Luo¹,

Liu²,

Zhang³

et al. 2004

Semicond. Sci. Technol.

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A single-crystalline Si/SiO 2 /poly-WSi x /Sub-Si structure has been successfully fabricated by a new method incorporating a standard smart-cut ® technique and a high temperature reaction between tungsten and silicon. Annealing at 800-1100 • C does not only strengthen the bonding of the wafers but also induces solid phase reaction of deposited tungsten and silicon. A poly-crystalline WSi x (1 < x < 2) layer with a tetragonal structure is formed below the buried oxide layer. Cross section images of TEM show three steep interfaces of the four layers. It is found that increasing the annealing temperature is in favour of decreasing the sheet resistance of tungsten silicide and improving the crystal quality of the top silicon layer. However, a spreading resistance profile measurement shows that annealing under high temperature ( 1000 • C) will induce diffusion of tungsten into the Si substrate which is confirmed by the EDX results and the reason is presented.

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Optical properties of bonded silicon silicide on insulator (S2OI): a new substrate for electronic and optical devices

Cited by 12 publications

References 2 publications

Vertical Bipolar Charge Plasma Transistor with Buried Metal Layer

Vertical Bipolar Charge Plasma Transistor with Buried Metal Layer

Thermal stability of CoSi₂layers implemented in a silicon-on-insulator substrate

Buried tungsten silicide layer in silicon on insulator substrate by Smart-Cut®

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Optical properties of bonded silicon silicide on insulator (S2OI): a new substrate for electronic and optical devices

Cited by 12 publications

References 2 publications

Vertical Bipolar Charge Plasma Transistor with Buried Metal Layer

Vertical Bipolar Charge Plasma Transistor with Buried Metal Layer

Thermal stability of CoSi2layers implemented in a silicon-on-insulator substrate

Buried tungsten silicide layer in silicon on insulator substrate by Smart-Cut®

Contact Info

Product

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Thermal stability of CoSi₂layers implemented in a silicon-on-insulator substrate