Operation and Control Scheme of a Five-Level Hybrid Inverter for Medium-Voltage Motor Drives

2019

Circuit Theory & Apps

Summary This paper presents a new structure of three‐phase five‐level inverter with a single direct current (DC) source for low‐ and medium‐voltage applications. The proposed configuration is built with a cascade connection of two‐level cells in a nested form and owns the advantages of a reduced number of passive components, total blocking voltage of the switches, and isolated DC sources. In order to make this topology attractive, a comparison is made with five‐level inverter topologies proposed for low‐ and medium‐voltage applications in recent years. The proposed circuit is powered using a single DC source and an auxiliary voltage‐balancing circuit (AVBC) to maintain the desired DC‐link capacitor voltages. A sinusoidal pulse width modulation (SPWM) scheme is implemented in field‐programmable gate array (FPGA), using Xilinx blocks developed in MATLAB/SIMULINK environment, to control the inverter switches. The performance of the proposed topology is verified through MATLAB simulation and prototype model for a step change in load. Finally, the experimental results are presented to validate the effectiveness of the proposed topology.

Section: Resultsmentioning

confidence: 99%

Section: Nested Three‐phase 5l Invertermentioning

confidence: 99%

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A new structure of three‐phase five‐level inverter with nested two‐level cells

2019

Circuit Theory & Apps

“…Recently, the FC‐based hybrid MLIs have become more prevalent because of their reduced device count. The topology proposed in Yu et al uses the cascade connection of a T‐type, three‐level inverter and an H‐bridge cell with an FC to produce the seven‐level output.…”

Section: Introductionmentioning

confidence: 99%

“…The requirement of high blocking voltage switches is reduced to half in Abhilash et al, which can generate seven‐level output with the same number of device count as like in Yu et al Because of the requirement of only one 4 V dc ‐rated switch in each phase, topology possess higher efficiency than Yu et al The common problem in both the topologies in Yu et al and Abhilash et al is the incomplete utilization of the DC‐link voltage. The topology proposed in Dao and Lee can make use of full DC‐link voltage with the use of an FC section. However, the output voltage levels in each phase are limited to only five, which results in a poor output voltage quality.…”

Section: Introductionmentioning

confidence: 99%

A new hybrid flying capacitor–based single‐phase nine‐level inverter

Int Trans Electr Energ Syst

2019

Multilevel inverters (MLIs) with reduced part count are becoming popular in the arena of medium voltage and medium power applications. This proposed topology owns the advantages of reduced number and voltage stress across the switching devices and higher efficiency. It also combines the method of utilizing full DC‐link voltage to improve the RMS output voltage. The proposed hybrid topology is constructed using three different sections consisting of a cascaded two two‐level inverter, H‐bridge with a flying capacitor, and single‐leg low‐frequency circuit. The complete modes of operation to generate 9‐level A. C voltage at the inverter output including the FC voltage balancing has been comprehensively presented. A comparison is constructed with the proposed and recent topologies in the literature to show the merits of the proposed configuration. The proposed topology is tested in MATLAB/SIMULINK environment and a scale‐down prototype has been developed in the laboratory. The feasibility of the proposed topology is verified through simulation and experimental results.

A three‐phase inverter circuit using half‐bridge cells and T‐NPC for medium‐voltage applications

2020

Circuit Theory & Apps

Three-phase single DC-source based multilevel inverter topologies play a pivotal role in industrial applications due to the reduced number of components and higher efficiency. This paper emphasizes the inverter for medium-voltage applications that employ a conventional three-phase T-type structure (T-NPC). The primary circuit of the proposed configuration consists of a T-NPC structure connected to the half-bridge cells at the top and the bottom sides of each phase. The secondary circuit consists of DC-link capacitors whose voltage balancing is attained through a separate voltage balancing circuit (VBC). Using the proposed configuration, the number of components and independent DC supplies are reduced compared with the conventional topologies such as a neutral point clamped (NPC) inverter, a flying capacitor (FC) inverter, and a cascaded H-bridge (CHB) inverter for the same number of output voltage levels. Hence, the proposed topology results in the reduction of weight, volume, and power losses of the inverter. A sine-triangle comparison method is employed in the field programmable gate array (FPGA) platform to generate the firing pulses of the circuit switches. The effectiveness of the proposed topology is verified with simulation studies and is experimentally validated with a scaleddown prototype.