Multilevel inverters (MLIs) with reduced part count are becoming popular in the arena of medium voltage and medium power applications. This proposed topology owns the advantages of reduced number and voltage stress across the switching devices and higher efficiency. It also combines the method of utilizing full DC‐link voltage to improve the RMS output voltage. The proposed hybrid topology is constructed using three different sections consisting of a cascaded two two‐level inverter, H‐bridge with a flying capacitor, and single‐leg low‐frequency circuit. The complete modes of operation to generate 9‐level A. C voltage at the inverter output including the FC voltage balancing has been comprehensively presented. A comparison is constructed with the proposed and recent topologies in the literature to show the merits of the proposed configuration. The proposed topology is tested in MATLAB/SIMULINK environment and a scale‐down prototype has been developed in the laboratory. The feasibility of the proposed topology is verified through simulation and experimental results.
Summary
Dual‐inverter‐driven open‐end winding brushless direct current motor (OEWBLDCM) drives are amenable for the implementation of some interesting fault‐tolerant features, which could find useful applications in low power electric vehicles (EVs). The power semiconductor switching devices in the dual‐inverter system are vulnerable to the development of open‐circuit faults (OCFs) and the short‐circuit faults (SCFs). This paper investigates the possibility of imparting complete fault‐tolerant capability to EVs, which employ OEWBLDC motors for propulsion. With the proposed dynamic post‐fault reconfiguration of the power circuit and the reconnection of the battery banks, it is possible to deliver the rated (i.e., 100%) post‐fault output power to the BLDC motor, despite the failure of a power semiconductor switching device (because of either an OCF or an SCF) in the dual‐inverter system. The feasibility evaluation of the proposed fault‐tolerant drive reveals that the aforementioned objectives are realizable at an affordable hike in the raw material cost of the propulsion system. Simulation studies and Experimental verification on a laboratory prototype validate the proposed fault‐tolerant OEWBLDCM drive.
Three-phase single DC-source based multilevel inverter topologies play a pivotal role in industrial applications due to the reduced number of components and higher efficiency. This paper emphasizes the inverter for medium-voltage applications that employ a conventional three-phase T-type structure (T-NPC). The primary circuit of the proposed configuration consists of a T-NPC structure connected to the half-bridge cells at the top and the bottom sides of each phase. The secondary circuit consists of DC-link capacitors whose voltage balancing is attained through a separate voltage balancing circuit (VBC). Using the proposed configuration, the number of components and independent DC supplies are reduced compared with the conventional topologies such as a neutral point clamped (NPC) inverter, a flying capacitor (FC) inverter, and a cascaded H-bridge (CHB) inverter for the same number of output voltage levels. Hence, the proposed topology results in the reduction of weight, volume, and power losses of the inverter. A sine-triangle comparison method is employed in the field programmable gate array (FPGA) platform to generate the firing pulses of the circuit switches. The effectiveness of the proposed topology is verified with simulation studies and is experimentally validated with a scaleddown prototype.
Summary
This paper presents a new structure of three‐phase five‐level inverter with a single direct current (DC) source for low‐ and medium‐voltage applications. The proposed configuration is built with a cascade connection of two‐level cells in a nested form and owns the advantages of a reduced number of passive components, total blocking voltage of the switches, and isolated DC sources. In order to make this topology attractive, a comparison is made with five‐level inverter topologies proposed for low‐ and medium‐voltage applications in recent years. The proposed circuit is powered using a single DC source and an auxiliary voltage‐balancing circuit (AVBC) to maintain the desired DC‐link capacitor voltages. A sinusoidal pulse width modulation (SPWM) scheme is implemented in field‐programmable gate array (FPGA), using Xilinx blocks developed in MATLAB/SIMULINK environment, to control the inverter switches. The performance of the proposed topology is verified through MATLAB simulation and prototype model for a step change in load. Finally, the experimental results are presented to validate the effectiveness of the proposed topology.
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