OpenCL-Based FPGA-Platform for Stencil Computation and Its Optimization Methodology

Waidyasooriya, Hasitha Muthumala; Takei, Yusuke; Tatsumi, Shunsuke; Hariyama, Masanori

doi:10.1109/tpds.2016.2614981

Cited by 65 publications

(77 citation statements)

References 22 publications

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“…FPGA accelerators for FDTD computation with simple boundary conditions are already implemented in previous works [5][6][7]. Although those works use different design methods such as OpenCL [16], HDL, or MaxCompiler [18], the basic architecture is very similar.…”

Section: Related Workmentioning

confidence: 99%

“…The works in [5][6][7] propose FPGA accelerators based on iteration-parallel computation. A high level design tool called MaxCompiler [18] is used in [5] to accelerate 3D FDTD computation.…”

Section: Related Workmentioning

confidence: 99%

“…A high level design tool called MaxCompiler [18] is used in [5] to accelerate 3D FDTD computation. OpenCL is used in [6,7] for 2D FDTD computation. Although these works use iteration-parallelism to increase the processing speed, they only support simple boundary conditions such as fixed boundaries where constants are used as the boundary data.…”

Section: Related Workmentioning

confidence: 99%

“…It consists of PCMs where each of which processes one iteration. This architecture is very similar to the one discussed in [5][6][7]. The difference is the structure of a PCM which can process both core and boundary data and also produces a regular output data stream.…”

Section: Data Flow Regulationmentioning

confidence: 99%

“…It is one of the most researched subjects and there are many proposals for new algorithms and accelerators. FPGA accelerators [4][5][6][7][8][9][10] are getting popular recently since they use deeply pipelined architectures by exploiting streaming data flows in FDTD computation. Streaming data flow computing is ideal for applications with low operational intensity [11] such as FDTD.…”

Section: Introductionmentioning

confidence: 99%

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OpenCL-Based FPGA Accelerator for 3D FDTD with Periodic and Absorbing Boundary Conditions

Waidyasooriya

Endo

Hariyama

et al. 2017

International Journal of Reconfigurable Computing

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Finite difference time domain (FDTD) method is a very poplar way of numerically solving partial differential equations. FDTD has a low operational intensity so that the performances in CPUs and GPUs are often restricted by the memory bandwidth. Recently, deeply pipelined FPGA accelerators have shown a lot of success by exploiting streaming data flows in FDTD computation. In spite of this success, many FPGA accelerators are not suitable for real-world applications that contain complex boundary conditions. Boundary conditions break the regularity of the data flow, so that the performances are significantly reduced. This paper proposes an FPGA accelerator that computes commonly used absorbing and periodic boundary conditions in many 3D FDTD applications. Accelerator is designed using a "C-like" programming language called OpenCL (open computing language). As a result, the proposed accelerator can be customized easily by changing the software code. According to the experimental results, we achieved over 3.3 times and 1.5 times higher processing speed compared to the CPUs and GPUs, respectively. Moreover, the proposed accelerator is more than 14 times faster compared to the recently proposed FPGA accelerators that are capable of handling complex boundary conditions.

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Section: Related Workmentioning

confidence: 99%