OpenCL-Based FPGA Accelerator for 3D FDTD with Periodic and Absorbing Boundary Conditions

Waidyasooriya, Hasitha Muthumala; Endo, Tsukasa; Hariyama, Masanori; Ohtera, Yasuo

doi:10.1155/2017/6817674

Cited by 7 publications

(5 citation statements)

References 20 publications

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“…For example, Hotspot 3-D benchmark [27] is often used to simulate the temperature distribution of 3-D LSIs [28]. Another example is FDTD simulation of fiber-optic cables [29] where the cross-section of a cable is extremely small compared to its length. Therefore, the size of dimensions corresponds to the cross section is small compared to the size of the dimension corresponds to the length.…”

Section: A Evaluation Using 2-d and 3-d Stencil Computation Benchmarksmentioning

confidence: 99%

Multi-FPGA Accelerator Architecture for Stencil Computation Exploiting Spacial and Temporal Scalability

Waidyasooriya

Hariyama

2019

IEEE Access

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After the introduction of the OpenCL-based FPGA accelerator design method, FPGAs are getting very popular among high-performance computing. The key to achieving high performance using FPGAs is to design pipelined accelerators. We can increase the pipeline depth beyond the border of one FPGA by connecting multiple FPGAs using high-speed QSFP (quad small form-factor pluggable) connectors. Such a deeply-pipelined accelerator using multiple FPGAs works similar to a single very large FPGA. In this paper, we propose a multi-FPGA accelerator architecture for stencil computation by scaling in spacial and temporal dimensions. According to the experimental results, we achieved performance up to 950 GFLOP/s using one FPGA and nearly doubled the performance using two FPGAs. We achieved a high power-efficiency with competitive performances compared to high-end GPUs.

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Section: A Evaluation Using 2-d and 3-d Stencil Computation Benchmarksmentioning

confidence: 99%

Multi-FPGA Accelerator Architecture for Stencil Computation Exploiting Spacial and Temporal Scalability

Waidyasooriya

Hariyama

2019

IEEE Access

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“…These methods include the combination of "spatial" and "temporal" blocking. Specifically, the OpenCL-based designs proposed in [21], [23], and [24] are among the successful works in the HLS domain for these blocking strategies. The problem of complex boundary conditions is still an open issue in hardware accelerators designed by HLS and the related works simplified the boundary conditions in favor of more parallelization.…”

Section: Discussionmentioning

confidence: 99%

“…Despite lower power consumption compared to GPU, the processing time could not be reduced for large grid sizes. Waidyasooriya et al in [21] extend the work in [20] to 3D FDTD by pipelining multiple FDTD iterations. Although they achieve better performance than CPU-or GPU-based designs, they only consider periodic structures for the boundary conditions.…”

Section: Related Workmentioning

confidence: 99%

FPGA Acceleration of 3D FDTD for Multi- Antennas Microwave Imaging Using HLS

Mansoori¹,

Casu

2021

IEEE Access

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Microwave Imaging (MI) for biomedical applications has attracted attention due to its harmless radiation compared to X-ray or MRI. One of the commonly used computing methods in MI is Finite Difference Time Domain (FDTD), which is executed several times in iterative loops, hence resulting in a high execution time. Although several hardware accelerators for FDTD have been recently introduced, they are not specifically designed for MI applications. In particular, only simple absorbing boundary conditions have been investigated, and the impact of dispersive materials on FDTD has not been considered. In this paper, we propose a multi-FPGA accelerator for 3D FDTD that is integrated in an MI algorithm, with Convolutional Perfectly Matched Layer (CPML) boundary conditions and an exact model for dispersive materials. By using High Level Synthesis (HLS), we obtain an optimized hardware accelerator that uses an efficient blocking method to reduce the data transfer time between external and local memories. We propose two alternative architectures that trade off performance and resource usage. In addition, our code, being developed at a high level, can also be run on GPUs whenever necessary. The results show that our multi-FPGA accelerator is superior to three similar GPU-based designs in terms of execution time and power consumption.

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“…Based on the traditional C language, the code written in OpenCL is highly portable [17]. Moreover, on account of the existence of the framework about OpenCL to FPGA, designers need neither to synthesize hardware description language nor to understand the hardware circuit structure, which greatly lowers the using threshold [18]. This paper proposed a parallel acceleration strategy of CNN based on FPGA with OpenCL by the use of Xilinx SDAccel.…”

Section: Introductionmentioning

confidence: 99%

Design of FPGA-Based Accelerator for Convolutional Neural Network under Heterogeneous Computing Framework with OpenCL

Luo

Qiao

et al. 2018

International Journal of Reconfigurable Computing

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CPU has insufficient resources to satisfy the efficient computation of the convolution neural network (CNN), especially for embedded applications. Therefore, heterogeneous computing platforms are widely used to accelerate CNN tasks, such as GPU, FPGA, and ASIC. Among these, FPGA can accelerate the computation by mapping the algorithm to the parallel hardware instead of CPU, which cannot fully exploit the parallelism. By fully using the parallelism of the neural network's structure, FPGA can reduce the computing costs and increase the computing speed. However, the development of FPGA requires great design skills. As a heterogeneous development platform, OpenCL has some advantages such as high abstraction level, short development cycle, and strong portability, which can make up for the lack of skilled designers. This paper uses Xilinx SDAccel to realize the parallel acceleration of CNN task, and it also proposes an optimizing strategy of single convolutional layer to accelerate CNN. Simulation results show that the calculation speed could be improved by adopting the proposed optimizing strategy. Compared with the baseline design, the strategy of single convolutional layer could increase the computing speed 14 times. Performance of the whole CNN task could be improved 2 times more than before, and the speed of image classification could attain more than 48 fps.

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OpenCL-Based FPGA Accelerator for 3D FDTD with Periodic and Absorbing Boundary Conditions

Cited by 7 publications

References 20 publications

Multi-FPGA Accelerator Architecture for Stencil Computation Exploiting Spacial and Temporal Scalability

Multi-FPGA Accelerator Architecture for Stencil Computation Exploiting Spacial and Temporal Scalability

FPGA Acceleration of 3D FDTD for Multi- Antennas Microwave Imaging Using HLS

Design of FPGA-Based Accelerator for Convolutional Neural Network under Heterogeneous Computing Framework with OpenCL

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