Open-Source RISC-V Processor IP Cores for FPGAs — Overview and Evaluation

Holler, Roland; Haselberger, Dominic; Ballek, D; Rössler, Peter; Krapfenbauer, Markus; Linauer, Martin

doi:10.1109/meco.2019.8760205

Cited by 36 publications

(22 citation statements)

References 18 publications

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“…There exist several further survey works comparing multiple RISC-V implementations [29], [37], [34] or processors of different ISAs [17], [32]. However, all are limited to 32 bit variants and target FPGA applications with soft-core processors only.…”

Section: Related Workmentioning

confidence: 99%

A comparative survey of open-source application-class RISC-V processor implementations

Dorflinger

Albers

Kleinbeck

et al. 2021

Proceedings of the 18th ACM International Conference on Computing Frontiers

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The numerous emerging implementations of RISC-V processors and frameworks underline the success of this Instruction Set Architecture (ISA) specification. The free and open source character of many implementations facilitates their adoption in academic and commercial projects. As yet it is not easy to say which implementation fits best for a system with given requirements such as processing performance or power consumption. With varying backgrounds and histories, the developed RISC-V processors are very different from each other. Comparisons are difficult, because results are reported for arbitrary technologies and configuration settings. Scaling factors are used to draw comparisons, but this gives only rough estimates. In order to give more substantiated results, this paper compares the most prominent open-source application-class RISC-V projects by running identical benchmarks on identical platforms with defined configuration settings. The Rocket, BOOM, CVA6, and SHAKTI C-Class implementations are evaluated for processing performance, area and resource utilization, power consumption as well as efficiency. Results are presented for the Xilinx Virtex UltraScale+ family and GlobalFoundries 22FDX ASIC technology. CCS CONCEPTS• Computer systems organization → System on a chip; Serial architectures.

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Section: Related Workmentioning

confidence: 99%

A comparative survey of open-source application-class RISC-V processor implementations

Dorflinger

Albers

Kleinbeck

et al. 2021

Proceedings of the 18th ACM International Conference on Computing Frontiers

View full text Add to dashboard Cite

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“…With the development of RISC-V, a large number of open-source processor cores have appeared in academic and commercial markets [28]. In recent years, the RISC-V processor has also been deeply studied and applied in the Internet of Things, neural networks, artificial intelligence, and so on [29][30][31][32].…”

Section: Related Workmentioning

confidence: 99%

DuckCore: A Fault-Tolerant Processor Core Architecture Based on the RISC-V ISA

Shan-cong

Bao

2021

Electronics

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With the development of large-scale CMOS-integrated circuit manufacturing technology, microprocessor chips are more vulnerable to soft errors and radiation interference, resulting in reduced reliability. Core reliability is an important element of the microprocessor’s ability to resist soft errors. This paper proposes DuckCore, a fault-tolerant processor core architecture based on the free and open instruction set architecture (ISA) RISC-V. This architecture uses improved SECDED (single error correction, double error detection) code between pipelines, detects processor operating errors in real-time through the Supervision unit, and takes instruction rollbacks for different error types, which not only saves resources but also improves the reliability of the processor core. In the implementation process, all error injection tests are passed to verify the completeness of the function. In order to better verify the performance of the processor under different error intensity injections, the software is used to inject errors, the running program is run on the FPGA (Field Programmable Gate Array), and the impact of the actual radiation environment on the architecture is evaluated through the results. The architecture is applied to three–five-stage open-source processor cores and the results show that this method consumes fewer resources and its discrete design makes it more portable.

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“…Some worthmention works are the highly customizable Rocket cores of the Berkeley architecture group [14], the high-performance 32-bit E-core series [15] and 64-bit U-core series [16] of IEICE Electronics Express, Vol.VV, No.NN, [1][2][3][4][5][6] the SiFive Inc., and the 32-bit RI5CY cores [17] and 64-bit Ariane cores [18] of the PULP-platform research group. For small low-power energy-efficient 32-bit RISC-V microprocessors, although there were plenty of IP cores presented in FPGAs as reviewed by R. Höller et al in June 2019 [19], silicon proof publications were still limited. The worthmention 32-bit RISC-V chip measurement publications can be listed are the Parallel Ultra-Low Power (PULP) SoC in 2016 [20], PULPv2 SoC in 2017 [21], the low-power microcontroller intended for Internet of Things (IoT) in 2016 [22] and 2017 [23], the FE310-G000 in 2017 [24], and the FE310-G002 in 2019 [25].…”

Section: Risc-v Is An Open-source Isa That Was First Presented By Thementioning

confidence: 99%

Low-power high-performance 32-bit RISC-V microcontroller on 65-nm silicon-on-thin-BOX (SOTB)

Hoang

Duran

Nguyen

et al. 2020

IEICE Electron. Express

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In this paper, a 32-bit RISC-V microcontroller in a 65-nm Silicon-On-Thin-BOX (SOTB) chip is presented. The system is developed based on the VexRiscv Central Processing Unit (CPU) with the Instruction Set Architecture (ISA) extensions of RV32IM. Besides the core processor, the System-on-Chip (SoC) contains 8KB of boot ROM, 64KB of on-chip memory, UART controller, SPI controller, timer, and GPIOs for LEDs and switches. The 8KB of boot ROM has 7KB of hard-code in combinational logics and 1KB of a stack in SRAM. The proposed SoC performs the Dhrystone and Coremark benchmarks with the results of 1.27 DMIPS/MHz and 2.4 Coremark/MHz, respectively. The layout occupies 1.32-mm 2 of die area, which equivalents to 349,061 of NAND2 gate-counts. The 65-nm SOTB process is chosen not only because of its low-power feature but also because of the back-gate biasing technique that allows us to control the microcontroller to favor the low-power or the high-performance operations. The measurement results show that the highest operating frequency of 156-MHz is achieved at 1.2-V supply voltage (V DD) with +1.6-V back-gate bias voltage (V BB). The best power density of 33.4-W/MHz is reached at 0.5-V V DD with +0.8-V V BB. The least current leakage of 3-nA is retrieved at 0.5-V V DD with −2.0-V V BB .

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Open-Source RISC-V Processor IP Cores for FPGAs — Overview and Evaluation

Cited by 36 publications

References 18 publications

A comparative survey of open-source application-class RISC-V processor implementations

A comparative survey of open-source application-class RISC-V processor implementations

DuckCore: A Fault-Tolerant Processor Core Architecture Based on the RISC-V ISA

Low-power high-performance 32-bit RISC-V microcontroller on 65-nm silicon-on-thin-BOX (SOTB)

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