DuckCore: A Fault-Tolerant Processor Core Architecture Based on the RISC-V ISA

Abstract

With the development of large-scale CMOS-integrated circuit manufacturing technology, microprocessor chips are more vulnerable to soft errors and radiation interference, resulting in reduced reliability. Core reliability is an important element of the microprocessor’s ability to resist soft errors. This paper proposes DuckCore, a fault-tolerant processor core architecture based on the free and open instruction set architecture (ISA) RISC-V. This architecture uses improved SECDED (single error correction, double error detection) code between pipelines, detects processor operating errors in real-time through the Supervision unit, and takes instruction rollbacks for different error types, which not only saves resources but also improves the reliability of the processor core. In the implementation process, all error injection tests are passed to verify the completeness of the function. In order to better verify the performance of the processor under different error intensity injections, the software is used to inject errors, the running program is run on the FPGA (Field Programmable Gate Array), and the impact of the actual radiation environment on the architecture is evaluated through the results. The architecture is applied to three–five-stage open-source processor cores and the results show that this method consumes fewer resources and its discrete design makes it more portable.

Soft-core processor integration based on different instruction set architectures and field programmable gate array custom datapath implementation

“…Table 4 shows the Artix-7 FPGA resource requirements for MicroBlaze, Cortex-M3, RISC-V, MIPS32 and HW_nMPRA_RTOS FPGA implementation architectures ( Włostowski, Serrano & Vaga, 2015 ; Li, Zhang & Bao, 2022 ; Tsai & Lee, 2022 ; Sarjoughian, Chen & Burger, 2008 ). It can be stated that the flip-flops and combinational logic requirements are convenient for the architecture proposed in this article, considering that HW_nMPRA_RTOS guarantees context switching in 1 ÷ 2 clock cycles and predictable response to interrupt events.…”

Hybrid Modular Redundancy: Exploring Modular Redundancy Approaches in RISC-V Multi-Core Computing Clusters for Reliable Processing in Space

“…STRV [46] implements TMR at a very fine granularity within a RISC-V core, replicating the circuitry and voting after each register to ensure correct processing. The Duck-Core [33] takes a different approach, implementing ECC in the pipeline registers and instruction rollback to allow re-execution of the last instruction in case a fault occurs. SHAKTI-F [23] uses a hybrid approach, using ECC for registers and memory while implementing DMR for the ALU within the processor's execution stage, ensuring the calculation is executed correctly.…”

“…In Table 2, we also compare our design with other works, such as SHATKI-F [23] and Duck Core [33]. The two works propose modifications to RISC-V cores' internal microarchitecture for pipeline rollback, showing a valuable approach that leads to just 3 clock cycles to perform a fault recovery and allowing for a single core to be reliable without the need for redundant grouping, thus saving resources.…”

Enhancing Fault Awareness and Reliability of a Fault-Tolerant RISC-V System-on-Chip

“…As seen in [15], the design of a lockstep RISC-V was proposed to address safety-critical applications. Other works presented hybrid solutions with similar strategies to find an optimal trade-off between performance, resource utilization, and reliability, such as [16][17][18]. In prior work, we proposed a fault-tolerant implementation of a RISC-V system [19,20] designed for FPGAs, known as HARV-SoC, where hybrid architectural redundancy techniques were applied, compared, and evaluated.…”