Onyx: A new heuristic bandwidth-constrained mapping of cores onto tile-based Network on Chip

Self Cite

Nowadays, with technology shrinking and the huge demand for supporting multiple applications has led designers to use multiple IP cores within a single chip. Therefore, the designers have proposed Networks-on-chip to overcome the problems of future complex systems. Mapping IPs directly affects NoC design parameters such as latency and power consumption. In this paper we present a power and performance aware mapping technique based on the combination of both the bandwidth-constrained and branch and bound concepts. Results have shown improvements of the latency and power consumption of our technique when compared to other popular NoC mappings.

Section: Simulation Resultsmentioning

confidence: 99%

Elixir: A new bandwidth-constrained mapping for Networks-on-chip

Reshadi

Khademzadeh

Reza

2010

Self Cite

“…The algorithm yields solutions by walking through the tree that represents the solution space. Janidarmian et al [14] propose a constructive heuristic algorithm (called Onyx) to assign cores to routers on a lozenge-shape path. In the algorithm, priorities are assigned to the cores based on the communication volume.…”

Section: Related Workmentioning

confidence: 99%

A novel two-phase heuristic for application mapping onto mesh-based Network-on-Chip

Wang

Liu

et al. 2016

With the growing complexity of embedded VLSI products, traditional System-on-Chip (SoC) are facing severe challenges in the aspects of communicating speed and scalability. Network-on-Chip (NoC) has emerged as a viable alternative. In NoC design, application mapping is one of the most holistic researching dimensions, which maps the cores in the application to the routers in the NoC platform. Application mapping problem usually aims to reduce communication cost and power consumption of the overall system. In this paper, we focus on application mapping onto mesh network, and propose a novel two-phase heuristic algorithm. The first phase attempts to explore the potential searching spaces, while the second phase focuses on exploiting the local optima within the searching basin. To verify the effectiveness of the algorithm, this paper performs a quantitative comparisons between our proposed method and the existing mapping methods under both real application and custom generated application benchmarks.

“…Hung et al [3] addressed NoC mapping problem with the aim of reducing the peak temperature and minimizing the communication cost by genetic algorithm. Janidarmian et al [4] employed Onyx algorithm for IP core mapping to minimize hop count between IP cores.…”

Section: Related Workmentioning

confidence: 99%

Thermal and competition aware mapping for 3D network-on-chip

Zhang

Yang

et al. 2012

Abstract:Three-dimensional network-on-chip (3D NoC), which combines NoC with 3D IC technology, offers several prominent advantages, including reduced overall interconnection length and design flexibility. However, it suffers from the high chip temperature problem. In the ciliated 3D Mesh architecture, the competition for the port of the router is fierce. A new temperature and network competitionaware mapping algorithm is proposed to reduce the peak temperature and decrease the network competition. The new algorithm can realize the multi-objective mapping and ensure a lower time complexity. Simulation results show that our method achieves an appropriate balance between peak temperature and network competition.