Online design bug detection: RTL analysis, flexible mechanisms, and evaluation

Constantinides, Kypros; Mutlu, Onur; Austin, Todd

doi:10.1109/micro.2008.4771798

Cited by 56 publications

(37 citation statements)

References 12 publications

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“…The design bugs (concurrent or complex) that could happen in the pipeline are considered. Various processor manufacturers' errata sheets are analysed by Constantinides et al (2008) and Narayanasamy et al (2006). The same is summarised in Table 2.…”

Section: Experimental Evaluationmentioning

confidence: 99%

On the field design bug tolerance on a multi-core processor using FPGA

Sriraman

Pattabiraman

2017

IJHPCN

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Abstract:In recent times, with increased transistor density, it is impossible to verify all the components exhaustively for different scenarios. This results in design bugs also known as extrinsic hardware faults to escape into the processor chip in spite of various levels of testing. Hence, handling design bugs efficiently on the field is a necessity in modern multi-core processors. In this paper, an architecture and algorithm for self-repairing of design bugs in the data path using FPGA is proposed. The FPGA is re-configured during the run-time to take over the functions of the faulty component. To verify the effectiveness of the proposed design a representative sample of five faults are injected and handled. The proposed design's area overhead and time overhead calculations are done using Cadence ncverilog and gem5 simulator respectively. The area overhead of the proposed design is < 1% and performance improvement is around 2.5% compared to the existing techniques.

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Section: Experimental Evaluationmentioning

confidence: 99%

On the field design bug tolerance on a multi-core processor using FPGA

Sriraman

Pattabiraman

2017

IJHPCN

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“…For example, according to the bug analysis of Intel Pentium 4 processor, which is one of the most representative industrial products, the number of detected bugs before releases is about 5809 [4]. Moreover, by analyzing its errata sheet, even after product release, there is still an average of 1.2 design bugs discovered per month [9]. However, codes of such industrial products are not available for us to conduct detailed evaluation.…”

Section: A Threats To Validitymentioning

confidence: 99%

Pre-Silicon Bug Forecast

Guo

Chen

Wang³

et al. 2014

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Abstract-The ever-intensifying time-to-market pressure imposes great challenges on the pre-silicon design phase of hardware. Before the tape-out, a pre-silicon design has to be thoroughly inspected by time-consuming functional verification and code review to exclude bugs. For functional verification and code review, a critical issue determining their efficiency is the allocation of resources (e.g., computational resources and manpower) to different modules of a design, which is conventionally guided by designers' experiences. Such practices, though simple and straightforward, may take high risks of wasting resources on bugfree modules or missing bugs in buggy modules, and thus could affect the success and timeline of the tape-out. In this paper, we propose a novel framework called pre-silicon bug forecast to predict the bug information of hardware designs. In this framework, bug models are built via machine learning techniques to characterize the relationship between design characteristics and the bug information, which can be leveraged to predict how bugs distribute in different modules of the current design. Such predicted bug information is adequate to regulate the resources among different modules to achieve efficient functional verification and code review. To evaluate the effectiveness of the proposed pre-silicon bug forecast framework, we conducted detailed experiments on several open-source hardware projects. Moreover, we also investigate the impacts of different learning techniques and different sets of characteristic on the performance of bug models. Experimental results show that with appropriate learning techniques and characteristics, about 90% modules could be correctly predicted as buggy or clean and the number of bugs of each module could also be accurately predicted.

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“…Unless two-state elements are used for each register, which leads to an excessive area overhead, the test environment needs to be restarted after each scan dump [18]. The scan registers with two-state elements are used in [19] for online detection of design bugs.…”

Section: A Hardware Structures For Post-silicon Debuggingmentioning

confidence: 99%

Automated debugging from pre-silicon to post-silicon

Dehbashi¹,

Fey²

2012

2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits &Amp; Systems (DDECS)

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Abstract-Due to the increasing design size and complexity of modern Integrated Circuits (IC) and the decreasing time-tomarket, debugging is one of the major bottlenecks in the IC development cycle. This paper presents a generalized approach to automate debugging which can be used in different scenarios from design debugging to post-silicon debugging. The approach is based on model-based diagnosis. Diagnostic traces are proposed as an enhancement reducing debugging time and increasing diagnosis accuracy. The experimental results show the effectiveness of the approach in post-silicon debugging.

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Online design bug detection: RTL analysis, flexible mechanisms, and evaluation

Cited by 56 publications

References 12 publications

On the field design bug tolerance on a multi-core processor using FPGA

On the field design bug tolerance on a multi-core processor using FPGA

Pre-Silicon Bug Forecast

Automated debugging from pre-silicon to post-silicon

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