Ongoing Evolution of DRAM Scaling via Third Dimension -Vertically Stacked DRAM -

Han, Jiwon; Park, S.H.; Jeong, Moon-Young; Lee, Kyusup; Kim, K.N.; Kim, H.J.; Shin, Jaeseung; Park, S.M.; Shin, Susanna; Park, S.W.; Lee, Kwang-Sik; Lee, J.H.; Kim, Shin Hyung; Kim, B.C; Jung, Minsu; Yoon, Il Young; Kim, Hyungtak; Park, K.J.; Kim, Y.K.; Kim, I.G.; Oh, Jung-Hun; Han, Sangyong; Kim, Bum Soo; Kuh, Bong Jin; Park, J.M.

doi:10.23919/vlsitechnologyandcir57934.2023.10185290

Cited by 13 publications

(5 citation statements)

References 1 publication

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“…With continuous device scaling to improve memory density, unit cells are reaching the scaling limit, and new approaches are proposed to preserve capacitance of DRAM capacitors and optimize the functions of high dielectric materials. [2][3][4] Currently, research focuses on the development of ultra-thin dielectric materials with a higher dielectric constant (high-k) and low-leakage currents. [5][6][7] With advent of such approaches, the process windows have become narrower with greater process step variability.…”

Section: Introductionmentioning

confidence: 99%

“…[5][6][7] With advent of such approaches, the process windows have become narrower with greater process step variability. 2,8 Therefore, measuring the critical dimensions (CD), elemental analysis of DRAM unit cell becomes increasingly critical and challenging. To address these demands, high volume, and high precision transmission electron microscopy (TEM) analysis has emerged as the new standard in the semiconductor industry.…”

Section: Introductionmentioning

confidence: 99%

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Automated TEM metrology and EDS characterization of plan view DRAM capacitors

Gnanasekaran,

Strauss,

Zhou

et al. 2024

Metrology, Inspection, and Process Control XXXVIII

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Capacitors play an essential role in dynamic random-access memory (DRAM) devices. With continuous DRAM device scaling, critical dimension measurements and elemental analysis of capacitor structures becomes more critical. Here, we present an automated TEM metrology and EDS characterization workflow for plan view DRAM capacitors. We utilized a Metrios 6 (Scanning) Transmission Electron Microscope ((S)TEM) equipped with an Ultra-X Energy Dispersive X-Ray Spectroscopy (EDS) detector to obtain high-quality analytical information of DRAM capacitors. The large solid angle of the Ultra-X detector provides approximately 3-4 times more X-ray counts than the previous generation Dual-X detector. Further, we show Ultra-X detector can characterize the elemental composition even on layers as thin as ~1 nm using low electron doses. Additionally, we demonstrate that the extended EDS acquisition induces elemental diffusion and structural alterations, leading to a ~4% reduction in the radius of certain DRAM layers. These findings underscore the importance of controlling the electron dose during imaging to ensure accurate, reliable, and reproducible CD measurements.

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Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Automated TEM metrology and EDS characterization of plan view DRAM capacitors

Gnanasekaran,

Strauss,

Zhou

et al. 2024

Metrology, Inspection, and Process Control XXXVIII

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“…This is accomplished by stacking device components in the Z direction that have been traditionally designed and fabricated in a side-by-side manner. For example, Complementary-Field Effect Transistor (CFET) technology has been suggested as a candidate for next generation logic by stacking p-and n-transistors [1,2,3]; 3D-Dynamic Random Access Memory (DRAM) is also being considered as a footprint reduction and scaling path for DRAM by stacking capacitors and bitlines (or wordlines) in 3D [4,5]; NAND has already moved to a 3D structure in the last decade using bitline stacking as well. [6,7] Stacking devices in 3D is challenging because it requires simultaneous engineering of fabrication processes at different levels of elevation.…”

Section: Introductionmentioning

confidence: 99%

Double self-aligned contact patterning scheme for 3D stacked logic and memory devices

Vincent,

Wen,

Ervin

2024

Advanced Etch Technology and Process Integration for Nanopatterning XIII

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This paper presents a new patterning scheme that allows self-alignment of active area contacts at different z-elevations. This patterning approach can be used for various types of 3D logic and memory devices. From an incoming structure using a stack of materials with different etch selectivity, some local metal braces are first introduced at certain targeted elevations and provide a first level of contact to active device materials. The brace formations require diverse etch selectivity for the selected dielectric materials, ultra-conformal metal deposition techniques for use on buried/covered structures, and anisotropic metal etching steps. A second level of contact is then made to access those braces by using via and cavity etches followed by metal fill. This multi-level contact patterning technique is further described in this paper by first using a generic example, and then by looking at two specific applications for logic and memory, with new CFET and staircase contacting schemes, respectively.

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“…A VS (vertically stacked) CAT (cell array transistor) is a prospective candidate that has the potential to improve the performance and power efficiency of electronic devices [14] . In 2023, a 3D stackable 1T1C DRAM structure based on vertically stacked SiGe/Si heterojunctions was reported at IMW [15] and VLSI [16] . Fig.…”

Section: Introductionmentioning

confidence: 99%

Multiple SiGe/Si layers epitaxy and SiGe selective etching for vertically stacked DRAM

Kong,

Lin,

Wang

et al. 2023

J. Semicond.

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Fifteen periods of Si/Si0.7Ge0.3 multilayers (MLs) with various SiGe thicknesses are grown on a 200 mm Si substrate using reduced pressure chemical vapor deposition (RPCVD). Several methods were utilized to characterize and analyze the ML structures. The high resolution transmission electron microscopy (HRTEM) results show that the ML structure with 20 nm Si0.7Ge0.3 features the best crystal quality and no defects are observed. Stacked Si0.7Ge0.3 ML structures etched by three different methods were carried out and compared, and the results show that they have different selectivities and morphologies. In this work, the fabrication process influences on Si/SiGe MLs are studied and there are no significant effects on the Si layers, which are the channels in lateral gate all around field effect transistor (L-GAAFET) devices. For vertically-stacked dynamic random access memory (VS-DRAM), it is necessary to consider the dislocation caused by strain accumulation and stress release after the number of stacked layers exceeds the critical thickness. These results pave the way for the manufacture of high-performance multivertical-stacked Si nanowires, nanosheet L-GAAFETs, and DRAM devices.

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Ongoing Evolution of DRAM Scaling via Third Dimension -Vertically Stacked DRAM -

Cited by 13 publications

References 1 publication

Automated TEM metrology and EDS characterization of plan view DRAM capacitors

Automated TEM metrology and EDS characterization of plan view DRAM capacitors

Double self-aligned contact patterning scheme for 3D stacked logic and memory devices

Multiple SiGe/Si layers epitaxy and SiGe selective etching for vertically stacked DRAM

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