One-Dimensional Analysis of Subthreshold Characteristics of SOI-MOSFET Considering
Quantum Mechanical Effects

Ikeno, Rimon; Itô, Hiroshi; Asada, Kunihiro

doi:10.1155/1998/23890

Cited by 1 publication

(1 citation statement)

References 4 publications

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“…Some explorations may propose that old innovation may show more noteworthy helplessness to such radiation; however such a conclusion may demonstrate untimely. Likewise with intentional electromagnetic interference [5], the reduced room for signal error may beat the common high vitality radiation hardness from smaller devices [6].…”

Section: Introductionmentioning

confidence: 99%

Low power radiation aware transistor level design using tri‐state inverter embedded non‐clock gating technique

Kamalakannan¹,

Venkatachalam²

2019

IET Circuits, Devices & Systems

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The effect of radiation on digital circuits in particularly complementary metal oxide semiconductor (CMOS) technology has been known since many years. The two most important radiation effects are total ionisation dose and single-event effects (SEEs). The complexity of circuit will increase depends on the number of gate inputs, which degrades the radiation to accelerate the total dose levels. The incremental dose level affects the circuit parameter failure, which affects the functionality of logic design. Many authors focus to reduce radiation effects with avoid function loss, but those extra efforts consume more power. In this study, a low power radiation aware circuit design is proposed. First, the physics-based modelling approach is used for compute radiation response of each component in the circuit. Tri-state inverter embedded non-clocked gating technique is proposed to eliminate unwanted latches and disables the inverter chain when the input data are kept unchanged, so redundant transitions of delayed clock signals. For simulation purpose, the authors applied their proposed technique in flip-flops and make it as more aware of radiation effects and power consumption. The performance of the proposed circuit design is analysed at 16 nm CMOS predictive technology model in terms of power delay product using HSPICE tool.

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Section: Introductionmentioning

confidence: 99%