One‐comparator counter‐based controller for synchronous DC/DC converters

Abstract

A low complexity, low component-count digital controller consisting of a single comparator and a digital counter is proposed for the purpose of providing control and voltage regulation for synchronous buck DC/DC converters used in voltage ripple insensitive applications. The system is modelled and analysed based on an averaged-circuit representation of the buck converter including the parasitic resistances of its passive and active components. The existence of limit cycles is investigated by using a describing function to represent the comparator and the pulse-width modulated generator. The simulation results are presented and are verified with experimental results for a 36 W prototype. The validity of the predicted performance of the proposed controller for higher loading conditions is thus confirmed.

High‐performance digital replica of analogue peak current mode control for DC–DC converter

“…In (5), T conv is the conversion time of the ADC. The exponential part is equal to one unit delay (z −1 ) in the discrete domain where T conv is the sampling period.…”

“…In a PCMC, the complex conjugate poles (CCPs) of the LC filter are eliminated; therefore, the phase declines more slowly than in voltage mode controlled (VMC) converters, which results in lower bandwidth of VMC versus PCMC [1]. In VMC, only the output voltage is used to regulate the converter [2][3][4][5], this method has the advantage of simplicity compared with PCMC. In PCMC, the outer voltage loop provides the reference for the inner current loop; the inner loop regulates the peak value of the inductor current with the current reference provided by the outer voltage loop.…”