2021 IEEE 39th VLSI Test Symposium (VTS) 2021
DOI: 10.1109/vts50974.2021.9441059
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On Workload-Aware DRAM Failure Prediction in Large-Scale Data Centers

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Cited by 7 publications
(1 citation statement)
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“…A data center is composed of large number of nodes, where each node consists of two sockets for the two CPUs. Each CPU has two integrated memory controllers (IMCs) that manage data in and out of memory within multiple channels [19]. An IMC is also called a memory chip controller (MCC) or memory controller unit (MCU).…”
Section: A Memory Structurementioning
confidence: 99%
“…A data center is composed of large number of nodes, where each node consists of two sockets for the two CPUs. Each CPU has two integrated memory controllers (IMCs) that manage data in and out of memory within multiple channels [19]. An IMC is also called a memory chip controller (MCC) or memory controller unit (MCU).…”
Section: A Memory Structurementioning
confidence: 99%