On-wafer CMOS transistors de-embedding method using two transmission lines of different lengths

Abstract

By using transmission line measurements of arbitrary characteristic impedance, this paper introduces an alternative method to de-embed parasitic structures such as pads and interconnection lines. The proposed method uses two uniform transmission lines of arbitrary characteristic impedance as calibration standard (L-L method). The two transmission lines have the same characteristic impedance, but different lengths. Experimental S-parameters data of on-wafer CMOS FETs de-embedded with the proposed L-L method, Mangan and the Pad-Open-Short De-embedded (PSOD) methods are compared. The S-parameter data deembedded with both methods the PSOD and the proposed two-tier L-L show high correlation. Therefore the proposed method is validated.

A Simple and Reliable Method to Extract The Electrical Equivalent Circuits of CMOS pads

“…Figure a shows the de‐embedded S‐parameters of a HVMOS FET at V GS = 3.0 V and V DS = 18.0 V, using and . The transistor is embedded in pads and interconnection lines of 54 μm of length, as depicted in Figure .…”

“…It is worth to comment that the pads were considered as ABCD matrices to perform the de‐embedded process, this means that in the case of the real part of the shunt admittance was considered negative as shown in Figure c. Now to verify whether a simple shunt admittance can be used as an EEC of the CMOS pad, de‐embedded S‐parameter data of the above transistor computed with and were used to reproduce the original measurement of the HVMOS FET. The characteristic impedance and γ of the interconnection line were computed according to the procedure described in .…”

“…Nevertheless, in the on‐wafer case, these conditions can fulfilled. Thus the objective in this work is to demonstrate the advantage of the two lines method to model accurately the CMOS pads by means of an electrical equivalent circuit (EEC). The knowledge of a CMOS pad is a valuable information in the design of radio frequency integrated circuit, nonetheless this information is not available in the design rules in spite of being of great help to develop better design.…”

“…To overcome this problem, the proposed method, which is based on , suggests an analytical method to obtain the EEC of the CMOS pads. The method assumes that the pads are symmetrical and reciprocal, and using ABCD matrices, it is possible to compute the elements of the EEC.…”

“…To verify whether a simple shunt admittance could be used as an EEC of the CMOS pad, de‐embedded S‐parameter data of an on‐wafer HVMOS FET computed with and were used to reproduce the original measurement of the HVMOS FET from 0.4 to 20 GHz. The results show that a shunt admittance is not sufficient to represents the CMOS pads.…”