On variable clock methods for path delay testing of sequential circuits

Implicit and Exact Path Delay Fault Grading in Sequential Circuits

“…The method is also exact. The grading methods in [3] cannot handle this generalization unless the underlying grading algorithm is invoked an exponential number of times to the length of the error propagation subsequence.…”

“…This guarantees sequential robustness [3]. A less restrictive sequentially non-robust approach assumes that only one error can be captured at a flip-flop during the PDF sensitization phase [3]. We will consider this method for comparison in the rest of the paper.…”

“…The most restricted method allows for error propagation along a path as long as it does not depend on any other error captured in another flip-flop. This guarantees sequential robustness [3]. A less restrictive sequentially non-robust approach assumes that only one error can be captured at a flip-flop during the PDF sensitization phase [3].…”

“…Existing techniques introduce assumptions during the error propagation phase to simplify the process at the expense of pessimism in the grading process [3,9,10]. The most restricted method allows for error propagation along a path as long as it does not depend on any other error captured in another flip-flop.…”

“…Testing for delay faults can be done so that all patterns are applied at the rated clock (at-speed), (see [8], among others) or using a variable clock method (see [3,9], among others). The latter is a pessimistic method where only one pattern in the test sequence is applied at a rated clock and will be the approach followed in this paper.…”