On the use of VHDL-based behavioral synthesis for telecom ASIC design

Genoe, M.; Vanoostende, P.; Wauwe, G. Van

doi:10.1145/224486.224514

Cited by 5 publications

(1 citation statement)

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“…Then it maps this description on the configurable architecture of the nano-network. The transformation of the high-level description of the function of the basic modules and of their interconnections into an RTL description does not represent a new research challenge as this task is similar to that addressed by high-level synthesis tools, like those described in [17]- [19].…”

Section: Circuit Synthesis Tool (Cs)mentioning

confidence: 99%

Towards a holistic CAD platform for nanotechnologies

Kolonis

Nicolaidis

2008

Microelectronics Journal

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Silicon-based CMOS technologies are predicted to reach their ultimate limits by the middle of the next decade. Research on nanotechnologies is actively conducted in a world-wide effort to develop new technologies able to maintain the Moore's law. They promise revolutionizing the computing systems by integrating tremendous numbers of devices at low cost. These trends will provide new computing opportunities, have a profound impact on the architectures of computing systems, and require a new paradigm of CAD. The paper presents a work in progress on this direction. It is aimed at fitting requirements and constraints of nanotechnologies, in an effort to achieve efficient use of the huge computing power promised by them. To move towards this goal we are developing CAD tools able to exploit efficiently the huge computing capabilities promised by nanotechnologies in the domain of simulation of complex systems composed by huge numbers of relatively simple elements.

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Section: Circuit Synthesis Tool (Cs)mentioning

confidence: 99%