An efficient methodology and semi-automated flow for design and validation of complex digital signal processing ASICS macro-cells

Tambour, L.; Zergainoh, Nacer-Eddine; Urard, Pascal; Michel, H; Jerraya, A.A.

doi:10.1109/iwrsp.2003.1207030

Cited by 1 publication

(3 citation statements)

References 16 publications

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“…The IP-based design methodology is based on designer's practice [17], [18]. The methodology, described in Fig.…”

Section: Overview Of Design Methodologymentioning

confidence: 99%

“…We define the generic F-IP as template described in Matlab hybrid representation [23], [17], [18]; many details are left open, only some signals which are relevant for the quantification are implemented in quantified integer. The generic F-IP blocks are stored in library.…”

Section: A Generic Dsp-ips Blocksmentioning

confidence: 99%

“…The delays may be managed by registers or by counters included in the control structure. The global approach is based on design practices that were already described in [17], [18]. The main contribution of this paper is a prototype implementation and experimentation of the approach.…”

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confidence: 99%

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IP-block-based design environment for high-throughput VLSI dedicated digital signal processing systems

Zergainoh

Popovici

Jerraya

et al. 2005

Proceedings of the 2005 Conference on Asia South Pacific Design Automation - ASP-DAC '05

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The Growing requirement on the correct design of a high performance DSP system in short time force us to use IP's in many design. In this paper, we propose an efficient IP block based design environment for high throughput VLSI Systems. The flow generates SystemC Register Transfer Level (RTL) architecture, starting from a Matlab functional model described as a netlist of functional IP. The refinement process inserts automatically control structures to treat delays induced by the use of RTL IPs. It also inserts a control structure to coordinate the execution of parallel clocked IP. The delays may be managed by registers or by counters included in the control structure. The experimentations show that the approach can produce efficient RTL architecture and allow a huge save of time. I. INTRODUCTIONAs the complexity of the high-throughput dedicated digital signal processing (DSP) systems increase, development efforts increase dramatically. At the same time, the market dynamics for electronic systems push for shorter development times [1]. In order to meet the design time requirements, a design methodology for VLSI dedicated DSP system that favors reuse and early error detection is essential. One idea, largely widespread and applied to design DSP systems, is to adopt a modular approach based on divide-and-conquer strategy (recursive) [20]. The global complexity of the system should be divided into subsystems (i.e. elementary signal processing functions), well known and of easily accessible complexity such as filter (FIR, IIR), fast Fourier transform (FFT), Viterbi decoder, etc. The system can be obtained by the hierarchical assembly of these common functions of signal processing (also known as IP blocks). The intellectual property (IP)-based design is obviously an important issue for improving not only design productivity, but also design from the higher-level abstraction.However, there are two major problems that designers encounter with the IP block-based design approach. The first problem (Problem 1) is the difficulty in using IPs blocks for high-throughput DSP systems that require various performances (throughput) or functions with non-standard algorithms. This is because VLSI DSP system cannot be parameterized for global performance and functions; for example, necessary processing cycles cannot be adjusted for IPs blocks. The second problem (Problem 2) comes from the interface between IPs blocks [19]. Designers have to design IPs blocks that can communicate according to the blocks' interface specification. When they connect two different IP blocks, they have to insert an extra interface circuitry in order to synchronize them. Area and delay overhead for circuitry cannot be neglected in some cases.A lot of research has been carried out on the IP-based design [2], [3], [4], [5], [6], [7], [8], [9], [10], [11], [12], [13]. Most of the research deals with IP-based SoC [10]-[13]. Problems on SoC synthesis are addressed in [21], where it is assumed that an external reference clock is supplied and the asynchronous commu...

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“…The IP-based design methodology is based on designer's practice [17], [18]. The methodology, described in Fig.…”

Section: Overview Of Design Methodologymentioning

confidence: 99%

Section: A Generic Dsp-ips Blocksmentioning

confidence: 99%

See 1 more Smart Citation

IP-block-based design environment for high-throughput VLSI dedicated digital signal processing systems

Zergainoh

Popovici

Jerraya

et al. 2005

Proceedings of the 2005 Conference on Asia South Pacific Design Automation - ASP-DAC '05

View full text Add to dashboard Cite

show abstract

An efficient methodology and semi-automated flow for design and validation of complex digital signal processing ASICS macro-cells

Cited by 1 publication

References 16 publications

IP-block-based design environment for high-throughput VLSI dedicated digital signal processing systems

IP-block-based design environment for high-throughput VLSI dedicated digital signal processing systems

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