On the use of mutations in Boolean minimization

Fišer, Petr; Hlavicka, J.

doi:10.1109/dsd.2001.952308

Cited by 3 publications

(3 citation statements)

References 12 publications

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“…[20] [21] [22] [23]. The FC-Min Boolean minimizer was introduced by Fišer and Kubátová in[24]; later, it was combined with the BOOM algorithm as the BOOM-II Boolean minimizer[25] [26].…”

mentioning

confidence: 99%

FPGA HW Accelerator of the First Step of Systematic Two-Level Minimization of Single-Output Boolean Function

Madoš¹,

Ádám²,

Bilanova³

et al. 2020

ACTA POLYTECH HUNG

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Boolean function minimization is an area important not only in the development and optimization of digital logic, but also in other research and development areas, such as, the optimization of control systems, simplifying program logic, artificial intelligence, etc. The aim of this paper is to present a hardware accelerated first step of the systematic minimization of single-output Boolean functionsthe generation of a set of prime implicants for both the disjunctive normal form (DNF) and the conjunctive normal form (CNF), having defined the OFF and ON sets andalternativelyalso the DC ("don't care") set. The proposed hardware accelerator is designed as combinational logic, described in VHDL. Its advantages include an extremely short prime-implicant-generation time in the order of ns and/or tens of nsin case of Boolean functions with small amount of input variablesand the possibility to generate the valid-prime-implicant set of Boolean functions having a defined number of input variables at a constant time, regardless of the cardinality of the ON or, eventually, the DC sets. However, these advantages come with a large spatial complexitythe number of utilized implementation elementsof the respective combinational module, generating the prime-implicant set. The authors verified the proposed design using Field Programmable Gate Array (FPGA) technology, implementing the hardware using a Xilinx Kintex-7 KC-705 Evaluation Kit development board.

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“…[20] [21] [22] [23]. The FC-Min Boolean minimizer was introduced by Fišer and Kubátová in[24]; later, it was combined with the BOOM algorithm as the BOOM-II Boolean minimizer[25] [26].…”

mentioning

confidence: 99%

FPGA HW Accelerator of the First Step of Systematic Two-Level Minimization of Single-Output Boolean Function

Madoš¹,

Ádám²,

Bilanova³

et al. 2020

ACTA POLYTECH HUNG

View full text Add to dashboard Cite

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“…In addition to it, for multi-output functions the primes are reduced into group implicants and then the group CP is solved. More details concerning these procedures can be found in [2,4].…”

Section: Principles Of the Boom Approachmentioning

confidence: 99%

“…The suggested partitioning algorithm is based on the BOOM minimization tool presented earlier [1][2][3][4][5]. It consists of two major phases: generation of implicants (prime implicants for single-output functions, group implicants for multi-output functions) and the subsequent solution of the covering problem (CP).…”

Section: Principles Of the Boom Approachmentioning

confidence: 99%

Minimization and partitioning method reducing input sets

Hlavicka

Fišer

Proceedings First IEEE International Workshop on Electronic Design, Test and Applications '2002

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The article describes a new Boolean minimization and single-level partitioning method based on the BOOM minimization system [6]. The minimization is performed with respect to the restrictions stated for the number of inputs and outputs of individual components and/or with the goal to reach load balancing for the inputs. The method can handle extremely large functions (up to thousands of input variables) in a very short time and its use is advantageous above all for highly unspecified functions, where the number of don't cares is large.

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Research on Technology of Mini-terms Optimization for Logic Function

Qiu

Chen

et al. 2009

2009 WRI World Congress on Software Engineering

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On the use of mutations in Boolean minimization

Cited by 3 publications

References 12 publications

FPGA HW Accelerator of the First Step of Systematic Two-Level Minimization of Single-Output Boolean Function

FPGA HW Accelerator of the First Step of Systematic Two-Level Minimization of Single-Output Boolean Function

Minimization and partitioning method reducing input sets

Research on Technology of Mini-terms Optimization for Logic Function

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