FPGA HW Accelerator of the First Step of Systematic Two-Level Minimization of Single-Output Boolean Function

Abstract

Boolean function minimization is an area important not only in the development and optimization of digital logic, but also in other research and development areas, such as, the optimization of control systems, simplifying program logic, artificial intelligence, etc. The aim of this paper is to present a hardware accelerated first step of the systematic minimization of single-output Boolean functionsthe generation of a set of prime implicants for both the disjunctive normal form (DNF) and the conjunctive normal form (CNF), having defined the OFF and ON sets andalternativelyalso the DC ("don't care") set. The proposed hardware accelerator is designed as combinational logic, described in VHDL. Its advantages include an extremely short prime-implicant-generation time in the order of ns and/or tens of nsin case of Boolean functions with small amount of input variablesand the possibility to generate the valid-prime-implicant set of Boolean functions having a defined number of input variables at a constant time, regardless of the cardinality of the ON or, eventually, the DC sets. However, these advantages come with a large spatial complexitythe number of utilized implementation elementsof the respective combinational module, generating the prime-implicant set. The authors verified the proposed design using Field Programmable Gate Array (FPGA) technology, implementing the hardware using a Xilinx Kintex-7 KC-705 Evaluation Kit development board.

DenseQMC: an efficient bit-slice implementation of the Quine-McCluskey algorithm

“…A similar idea was proposed already in [19], but not sufficiently developed and detailed. Furthermore, we also employ and develop the idea of [5] to consider the full possible state of size 3 n packed in a dense bit-vector similar to implementations in [14,21]. In addition, the core of the algorithm essentially describes a Boolean circuit, reminiscent of hardware accelerators proposed in [13,14].…”

“…We do not provide explicit comparison with existing implementations, since we could not find any competitive implementation and/or sufficient performance information. For a rough comparison, the work [10] reports 34 seconds for a function with n = 11, [5] reports 5 seconds for a very sparse function with n = 15, all of which are done instantly by any of our implementations; [14] gives mixed CPU/GPU timings such as 1000 seconds and 10 GiB RAM for the dense case of n = 20, 10 minutes for an n = 24-bit function of density 70%, 2000 seconds for an n = 28-bit function of density 30%, close to 10 6 seconds on an n = 32-bit function of density 42% using disk storage (due to ambiguous reports and absence of available implementation, it is difficult to provide a clear comparison). Note that the dense case is often occurring in practice when optimizing a CNF formula of a sparse function, for example, [2] report 2 hours of work for the case of n = 16 and 82%-dense function, appearing in cryptographic applications.…”