On the use of approximate adders in carry-save multiplier-accumulators

Esposito, Darjn; De, Davide; Napoli, Ettore; Petra, Nicola; Strollo, A.G.M.

doi:10.1109/iscas.2017.8050437

Cited by 21 publications

(7 citation statements)

References 12 publications

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“…Furthermore, since the home BS selection of the proposed cell search is on the BS side, it offloads the computational cost from the UEs to BSs. To evaluate such offloading in terms of the energy consumption saved by the UE, using Table 1 of [39], we can consider that the energy consumption to perform a single complex multiplication is 1.510 -3 nJ in the circuit made by the 28nm technology. It follows that the energy consumptions to complete the cell search of a UE are 29 J and 40 J for the code-based and proposed network resolved cell search approaches, respectively.…”

Section: Computational Complexity and Energy Consumption Analysismentioning

confidence: 99%

A Novel Network Resolved and Mobile Assisted Cell Search Method for 5G Cellular Communication Systems

et al. 2022

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When the user equipment (UE) is turned on, it first needs to perform an initial cell search procedure before it can communicate with the base station (BS). However, this procedure must deal with the initial time and frequency synchronization and search for the appropriate home BS for services. In conventional cell search methods, the entire cell search process is carried out on the UE, where the computational requirement can lead to additional overhead and power consumption of the UE. Therefore, aiming to help UEs offloading their overhead to BSs, we in this paper propose a novel cell search method, called Network Resolved and Mobile Assisted Cell Search, which can achieve our goal by letting the BSs be the main performers for deciding the appropriate BSs for connection and letting UEs only be the assistants of the cell search process. The implementation details and analysis of the proposed cell search approach are provided along with the numerical simulations. Results show that our proposed cell search not only can offload the computational overhead, but it also outperforms the conventional code-based cell search approach in terms of the cell search error probability with similar overall network energy consumption.INDEX TERMS initial cell search, cellular systems, multipath division multiple access (MDMA), universal pilot, base station.

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Section: Computational Complexity and Energy Consumption Analysismentioning

confidence: 99%

A Novel Network Resolved and Mobile Assisted Cell Search Method for 5G Cellular Communication Systems

et al. 2022

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“…These compressors are used in the decrease the partial products generated in multiplication process and these are implemented to add the multiple partial products into two partial outputs along with a carry propagating bit. According to the multiplier bit length these compressors are designed to reduce the partial product count [9]. Due to these approximate compressors the addition of partial products is done easily.…”

Section: Design Of Compressorsmentioning

confidence: 99%

“…The exact multipliers are consuming high speed and require huge delay to obtain exact outputs. Due to these exact multipliers, there is only one major defect is that it can't optimize further while using multiple techniques [9]- [11]. Hence for the image processing and signal processing applications accept the errors data and gives the modulated signals.…”

Section: Introductionmentioning

confidence: 99%

Low-power and high-speed approximate multiplier using higher order compressors for measurement systems

et al. 2022

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At present, approximate multipliers are used in the image processing applications. These approximate multipliers are designed with the help of higher order compressors to decrease the number of addition stages involved for the lessening stages. The approximate computing is the best technique to improve the power efficiency and reduce delay path. With the use of approximate computing multiple compressors are designed. In this paper, 10:2 compressors are designed and implemented in the 32-bit multiplier and compared with the exact 32-bit multipliers. The proposed higher bit compressors along with the lower bit compressors are implemented to reduce the delay of the design. This type of digital circuits has much significance in measurement technologies, for enabling fast and accurate measurements. With the use of approximate compressors, the result may be ineffective, but the power consumption and delay are getting reduced. Hence, these proposed multipliers are only implemented the digital signal processing applications, where there is need for combining two or more signals. The proposed multiplier is used for implementing FIR filter resulted 27 ns delay which is far better than the exact multiplier having 119 ns. These multipliers also used in image processing applications and PSNR of image has been employed.

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“…Some prior works aim to decrease the energy consumption or latency by applying approximate compressors to the different levels of partial product accumulation [1] [5]. The architecture of the adder being used for accumulating the partial product affects the energy consumption of the multiplier [4]. Thus, employing approximations for adders can further reduce the energy consumption of a multiplier.…”

Section: Introductionmentioning

confidence: 99%

scaleTRIM: Scalable TRuncation-Based Integer Approximate Multiplier with Linearization and Compensation

Farahmand¹,

Mahani²,

Ghavami³

et al. 2023

Preprint

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Approximate computing (AC) has become a prominent solution to improve the performance, area, and power/energy efficiency of a digital design at the cost of output accuracy. We propose a novel scalable approximate multiplier that approximates the multiplication of two operands using fitted linear functions with two inputs, referred to as linearization. Multiplication operations can be completely replaced by addition and bit-wise shift by using linearization. Moreover, it utilizes a lookup table-based compensation unit as a novel error-reduction method. Input operands are truncated to a reduced bitwidth representation (e.g., h bits) based on their leading one positions. Then, a curve-fitting method is employed to map the product term to a linear function, and a piecewise constant error-correction term is used to reduce the approximation error. In order to compute the piecewise constant error-compensation term, we divide the function space into M segments and average the errors within each segment. The multiplier supports various degrees of truncation and error-compensation to exploit accuracy-efficiency trade-off. The proposed approximate multiplier offers better error metrics such as mean and standard deviation of absolute relative error (MARED and StdARED) compare to a state-of-theart integer approximate multiplier. The proposed approximate multiplier improves the MARED and StdARED by about 38% and 32% when its energy consumption is about equal to the stateof-the-art approximate multiplier. Moreover, the performance of the proposed approximate multiplier is evaluated in image classification applications using a Deep Neural Network (DNN). The results indicate that the degradation of DNN accuracy is negligible especially due to the compensation properties of our approximate multiplier.

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On the use of approximate adders in carry-save multiplier-accumulators

Cited by 21 publications

References 12 publications

A Novel Network Resolved and Mobile Assisted Cell Search Method for 5G Cellular Communication Systems

A Novel Network Resolved and Mobile Assisted Cell Search Method for 5G Cellular Communication Systems

Low-power and high-speed approximate multiplier using higher order compressors for measurement systems

scaleTRIM: Scalable TRuncation-Based Integer Approximate Multiplier with Linearization and Compensation

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