On the thermal characterization of an exposed top quad flat no-lead package

Abstract

The relentless trend of ever increasing integrated circuit chip functionality and decreasing chip dimensions for miniaturization of products have led to intense heat dissipation in IC chips. The problem of effective cooling of chips at an acceptable cost is now becoming an urgent issue [1]. Leadframe CSP package is a promising candidate for portable wireless applications such as Bluetooth and home RF. It offers attractive attributes in terms of a near CSP footprint, good electrical and thermal characteristics. This paper addresses the concern and possible solution when conducting thermal characterization of an Exposed Top Quad Flat No-Lead (et-QFN) package, which had successfully been developed and qualified in United Test and Assembly Center (UTAC). Studies were performed to assess the impact of JEDEC test board types, with/without metal housing under different air speeds using commercial CFD code and the same is validated with experiment results. FA tools were used to pinpoint factors that are to blame for the significant measurement errors observed. Good agreement could be achieved between simulation and testing results when these factors were included into the CFD models. Recommendations regarding SMT and modification of specifications of 2s2p JESD51 PCB are proposed and discussed.

The process development and reliability study of low cost Area Array QFN packaging technology

“…Thermal properties of QFN were studied extensively [1,6]. In present study, we make comparison of QFN and BGA packages with the same pin count of 256.…”