On the Scaling of Flash Cell Spacer for Gate Disturb and Charge Retention Optimization

Assessment of distributed-cycling schemes on 45nm NOR flash memory arrays

“…from 8 to 10, we attributed the observed V T -drifts on fresh arrays to small charge displacements in the ONO interpoly dielectric during positive gate-stresses. In particular, the nitride layer of the ONO stack may act as a trapping layer for electrons during cell operation, increasing cell V T [37], [38]. During positive gate stresses, these trapped electrons can slightly move inside the nitride, getting closer to the control gate and, thus, leading to a negative V T -shift, as previously reported for 90 nm NOR technologies [39].…”

“…6, where the V T distributions of a 2bit/cell MLC technology are shown: during on-field operation, cell V T is compared against 3 read levels R1 -R3 but, in our experimental procedure, a WL stress higher than R3 is required to measure V T of cells belonging to L3. Thus, a careful investigation of the impact of stress field during V T acquisition is mandatory [33]- [37]. Disturbs arising from the V T map acquisition were evaluated by performing bake tests on fresh arrays, simply omitting the cycling phase in the experimental procedure depicted in Fig.…”

Reliability of NAND Flash Memories: Planar Cells and Emerging Issues in 3D Devices

“…Data for the V T shift as a function of the number of reads feature different dependences [255,256], while raw bit-error rate (RBER) data vs. the number of reads reveal a linear dependence whose slope increases with cycles [60,255,257], with a higher BER observed on SLCs than on MLCs. As with SILC, several process optimization [258,259], voltage tuning [255,260] or system-level correction [261] proposals have been put forward to alleviate the issue.…”