On the Practicality of Using Intrinsic Reconfiguration for Fault Recovery

Abstract

Evolvable hardware combines the powerful search capability of evolutionary algorithms with the flexibility of reprogrammable devices, thereby providing a natural framework for reconfiguration. This framework has generated an interest in using evolvable hardware for fault-tolerant systems because reconfiguration can effectively deal with hardware faults whenever it is impossible to provide spares. But systems cannot tolerate faults indefinitely, which means reconfiguration does have a deadline. The focus of previous evolvable hardware research relating to fault-tolerance has been primarily restricted to restoring functionality, with no real consideration of time constraints. In this paper we are concerned with evolvable hardware performing reconfiguration under deadline constraints. In particular, we investigate reconfigurable hardware that undergoes intrinsic evolution. We show that fault recovery done by intrinsic reconfiguration has some restrictions, which designers cannot ignore.

Scalable FPGA Refurbishment Using Netlist-Driven Evolutionary Algorithms

“…The recovery times reported in Table IX are calculated, where the fitness evaluation is the main time consuming part of the evolutionary refurbishment process as pointed out in [15]. If the time to download a configuration onto the FPGA for evaluating the fitness of an individual is denoted by t d and the time to do the fitness evaluation itself is denoted by t f .…”

“…Further, assume g generations are required to find a refurbished FPGA configuration according to the user criterion. Then, the total reconfiguration time T r consumed by the evolutionary algorithm with a population size of |P | is given by T r = g|P |(t d + t f ), which can be approximately considered equal to the recovery time [15].…”

Evolutionary synthesis of low-sensitivity digital filters using adjacency matrix

“…The sensitivity of the transfer function magnitude with respect to the multipliers is obtained differentiating (19):…”

“…These algorithms have recently attracted the researcher's attention due to their success in synthesizing large classes of analog [5][6][7][8][9][10][11][12][13] and digital [14][15][16][17][18] circuits. In contrast with traditional synthesis methods, evolutionary synthesis has the desirable property of including the circuit topology as a variable of overall synthesis problem, opening the opportunity of approaching some complex circuit design issues as selfadaptation, self-repairing and self-reconfiguration [19,20].…”

Practical Concerns When Evolving Circuits Impervious to Anticipated Faults

“…Any discussion about fault tolerance cannot ignore the fact that fault recovery is inherently a real-time process [6]. All faults must be corrected before some specified deadline to prevent other faults from happening.…”