On the models for asynchronous circuit behaviour with OR causality

Yakovlev, Alex; Kishinevsky, Michael; Kondratyev, A.; Lavagno, Luciano; Pietkiewicz-Koutny, Marta

doi:10.1007/bf00122082

Cited by 38 publications

(20 citation statements)

References 30 publications

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“…The reason that the gate becomes excited without waiting for transition x * after relaxing the arc x * ⇒ y * is that transition y * could make another clause in f o↑ or f o↓ become true. This is called OR-causality in [63] and [64]. This is not a hazard because the arc x * ⇒ y * indicates that (in gate y) x * is acknowledged by y * , so when y * arrives, x * must have occurred (even though x * has not propagated to gate o yet).…”

Section: Classication Of Arcs In the Local Stgmentioning

confidence: 99%

Redressing timing issues for speed-independent circuits in deep submicron age

Mak

Yakovlev

2011

2011 Design, Automation &Amp; Test in Europe

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Signature from head of PhD committee:ii )>IJH=?J With continued advancement in semiconductor manufacturing technologies, process variations become more and more severe. These variations not only impair circuit performance but may also cause potential hazards in integrated circuits (IC). Asynchronous IC design, which does not rely on the use of an explicit clock, is more robust to process variations compared to synchronous design and is suggested to be a promising design approach in deep-submicron age, especially for low-power or harsh environment applications.However, the correctness of asynchronous circuits is also becoming challenged by the shrinking technology. The increased wire delays compared to gate delays and threshold variations could bring glitches into the circuit.This work proposes a method to generate a set of sucient timing constraints for a given speed-independent circuit to work correctly when the isochronic fork timing assumption is lifted into a weaker timing assumption. The complexity of the entire process is polynomial to the number of gates. The generated timing constraints are relative orderings between the transition events at the input of each gate and the circuit is guaranteed to work correctly by fullling these constraints under the timing assumption.The benchmarks show that both the number of total constraints and the constraints that are only needed to eliminate strong adversary paths are reduced by around 40% compared to those suggested in the current literature, thus claiming the weakest formally proved conditions. I would like to thank Dr. Terrence Mak for his education on research in both technique aspect and non-technique aspect.

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Section: Classication Of Arcs In the Local Stgmentioning

confidence: 99%

Redressing timing issues for speed-independent circuits in deep submicron age

Mak

Yakovlev

2011

2011 Design, Automation &Amp; Test in Europe

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“…Early evaluation allows an asynchronous component to compute its output before all of its input values are available. It is a more practical restriction of the OR-causality precedence relation for which Yakovlev et al provide formal models and implementations for speed-independent asynchronous circuits in [26] and [27]. Early evaluation has been applied to phased logic at different granularity levels by Reese et al [28], [29] and to the optimization of pipelined asynchronous logic by both Brej and Garside [30] and, more recently, by Ampalam and Singh [31].…”

Section: Related Workmentioning

confidence: 99%

Leveraging Local Intracore Information to Increase Global Performance in Block-Based Design of Systems-on-Chip

Carloni

2009

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Abstract-Latency-insensitive design is a methodology for system-on-chip (SoC) design that simplifies the reuse of intellectual property cores and the implementation of the communication among them. This simplification is based on a system-level protocol that decouples the intracore logic design from the design of the intercore communication channels. Each core is encapsulated within a shell, a synthesized logic block that dynamically controls its operation to interface it with the rest of the SoC and absorb any latency variations on its I/O signals. In particular, a shell stalls a core whenever new valid data are not available on the input channels or a downlink core has requested a delay in the data production on the output channels. We study how knowledge about the internal logic structure of a core can be applied to the design of its shell to improve the overall system-level performance by avoiding unnecessary local stalling. We introduce the notion of functional independence condition (FIC) and present a novel circuit design of a generic shell template that can leverage FIC. We propose a procedure for the logic synthesis of a FIC-shell instance that is only based on the analysis of the intracore logic and does not require any input from the designers. Finally, we present a comprehensive experimental analysis that shows the performance benefits and limited design overhead of the proposed technique. This includes the semicustom design of an SoC, an ultrawideband baseband transmitter, using a 90-nm industrial standard cell library.Index Terms-Finite state machines (FSMs), latency-insensitive design (LID), logic synthesis, sequential logic optimization, system-level design, system-on-chip (SoCs).

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“…Usual Petri nets are not capable of modeling early evaluation, since the enabling of transitions is based on AND-causality, i.e., all input conditions must be asserted. Causal Logic Nets from [43] extend Petri nets to allow transition enabling triggered by arbitrary logic guards associated with transitions. This section presents a new model of nets, called multi-guarded nets (GN), with the power of modeling early evaluation that associate with a single transition multiple logic guards selected non-deterministically.…”

Section: Motivation and Examplesmentioning

confidence: 99%

Elasticity and Petri Nets

Cortadella

Kishinevsky

Bufistov

et al. 2008

Transactions on Petri Nets and Other Models of Concurrency I

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Abstract. Digital electronic systems typically use synchronous clocks and primarily assume fixed duration of their operations to simplify the design process. Time elastic systems can be constructed either by replacing the clock with communication handshakes (asynchronous version) or by augmenting the clock with a synchronous version of a handshake (synchronous version). Time elastic systems can tolerate static and dynamic changes in delays (asynchronous case) or latencies (synchronous case) of operations that can be used for modularity, ease of reuse and better power-delay trade-off. This paper describes methods for the modeling, performance analysis and optimization of elastic systems using Marked Graphs and their extensions capable of describing behavior with early evaluation. The paper uses synchronous elastic systems (aka latency-tolerant systems) for illustrating the use of Petri Nets, however most of the methods can be applied without changes (except changing the delay model associated with events of the system) to asynchronous elastic systems.

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On the models for asynchronous circuit behaviour with OR causality

Cited by 38 publications

References 30 publications

Redressing timing issues for speed-independent circuits in deep submicron age

Redressing timing issues for speed-independent circuits in deep submicron age

Leveraging Local Intracore Information to Increase Global Performance in Block-Based Design of Systems-on-Chip

Elasticity and Petri Nets

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